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Martin Thompson

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1487.04 (4,454,104th)
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VHDL read generic default value -0.02
Multidimensional memory with generic data width VHDL 0.00
warning in post route simualtion 0.00
matlab to vhdl code generation. Function rand is not supported in f... 0.00
Serial communication with LPC1786 -0.28
Error : Non-static loop limit exceeded -0.63
Vhdl with no clk -0.12
VHDL UCF - how to define a constraint that has no pin? 0.00
VHDL Simple code optimization -1.06
Beaglebone C/C++ programing in windows 7 -0.01
Interfacing 32 bit data to spartan3E kit by using RS 232 interface 0.00
Is a <= a + 1 a good practice in VHDL? -0.93
Is it generally possible to uniquely identify an individual MCU (fo... -1.28
What to do when a latch cannot be avoided? -1.19
Configuring cross-compiler to use custom library search path 0.00
using generic string in VHDL report 0.00
What VHDL datatype should I use for a memory address? +0.56
Design vision error OPT-1206 AFTER VHDL 0.00
VHDL: creating a very slow clock pulse based on a very fast clock -0.49
Python: CRC implementation using xor and shift registers -1.94
Pointer dereference in VHDL +0.56
How to debug after implementation? My code that works perfectly in... -1.70
Unsigned operation need signed variable or what in VHDL -0.52
Array literals in VHDL -0.52
VHDL: How to check selected bits of a vector 0.00
Optimizing My Verilog Code for Feedforward Algorithm in Neural Netw... +0.30
Embedded: C Coding for Ctrl-C interrupt in u-boot terminal -0.35
C51 Compiler - Write to xdata +0.45
How to fix Xilinx ISE warning about sensitivity list? +0.47
why TI starterware examples do not clear correctly BSS segment when... +0.48
Convert 8 bytes uint8_t array to 4 bytes array -0.03
use of 'fopen' on non OS Arm board +1.96
reading a VHDL output through PLB bus by using Microblaze c code -0.03
Hardware Bringup - install uboot in fresh board -0.27
Is it possible to create a HW based synthesizer for RTL? +0.46
VHDL: Add list of numbers using loop -0.03
Leading zeros counter -0.05
memory leak in an embedded system +0.49
Reading live RAM variables from a Micro controller in VB.net -0.89
Library Retarget File and Low Level I/O Routines in Keil RealView u... 0.00
tools to study real time scheduling in embedded systems -0.02
Do x86 processors transmit/receive data in little endian format ove... -0.08
VHDL bit rotation function syntax error? -0.52
verilog to FSM convert -0.28
How to: multidimensional arrays in vhdl -0.54
variable PWM setting in PIC24FJ64GA002 0.00
Does there exist an open source tool for simulating a CAN bus with... 0.00
VHDL alternative submodule architecture for simulation +0.05
Mod error due to input vector in vhdl -0.27
Non-static loop limit exceeded +0.14