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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 ... 5 6 7 8 9 ... 12

Title	Δ
Any function instead of sprintf() in C? code size is too big after...	+1.03
What's CRC with 64b in and 32b out?	0.00
Synthesis and Simulation Independent Clock Divider	+0.46
How Can i eliminate inout signal for my vhdl Adder?	-1.92
How to decode an unsigned integer into BCD use VHDL	-0.04
Designing a Combinational Shift Operator in VHDL	-0.53
VHDL : Library required	+0.47
Signals and Variables in VHDL	0.00
VHDL: use the length of an integer generic to determine number of s...	-0.54
In a structural VHDL ROM, how can I have multiple word lines drive...	+0.46
What causes "Data type not implemented for operator 'COMPARE'&...	-0.54
Moving data between processes in Spartan 3	-0.29
Chess engine with FPGA	-0.54
If Statement VHDL	+0.47
How to shift a std_logic_vector by std_logic_vector using concatena...	-0.04
Good Practice (for FSMs): BUSY or IDLE	-0.74
How can I simplify generics usage for ports in VHDL?	-1.64
Shared variable in VHDL	0.00
changing control variable in Case statement in VHDL	-0.49
VHDL 4-Bit Multiplier: use_dsp48 and Gated clock	+0.47
Is there a way to force PMULHRSW to treat 0x8000 as 1.0 instead of...	0.00
optimizing VHDL code	+0.46
relationship between flopping and meta-stability	0.00
how are process'es evaluated in practice	-0.55
timing constraints	-0.47
Is there a tool/simulator that supports line coverage for SystemVer...	+0.26
Make a simple circuit to dissipate power in VHDL	+0.46
Design VHDL state machine for initialization	-1.30
Best VHDL design practice	-0.28
Delay a signal in vhdl	+0.03
How to specify an integer array as generic in VHDL?	-0.54
Division in verilog	-1.27
How does tvtak work for real-time content recognition for TV broadc...	0.00
Why do VHDL attribute calls require a process?	0.00
system verilog /oop	-0.54
LPC 1768 CAN bus off error	0.00
VHDL Array Type Case Handling	0.00
Defining initial value for Matrix2D in VHDL	0.00
How often does processor cache flush?	-0.68
Continuous data streaming from Arduino to Python (failing readlines)	0.00
VHDL IEEE standard lib vs. component	0.00
profiling, How to avoid FPU (hardware) in VS pro 2008 or 2012RC and...	0.00
Signal or variable counter inside a generate statement	+0.46
How to generate bitstream (.bin) file using Synplify	0.00
Generating an OUT from an INOUT	0.00
VHDL beta function	-0.54
Why isn't this VHDL inferring BRAM in XST?	+0.21
working on a project using altera DE2-115, the project involves sho...	0.00
How can I estimate if a feature is going to take up too many resour...	-2.02
Fill area between two connected components in MATLAB	-1.93