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Martin Thompson

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1487.04 (4,454,104th) 		Reputation
14,667 (9,652nd)
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Title Δ
How can I check if a VHDL Integer is even or odd? -0.87
Xilinx Error: Place 1018 message 0.00
How do I deinterlace an image in Python? 0.00
how can i know if my code is Synthesizable? [Verilog] 0.00
Is it possible to reuse a CryptVerifySignature() hash object? 0.00
IEEE Float type to std_logic_vector conversion 0.00
What are some practical applications of an FPGA? -1.32
short 2 different Ports in MSP430 software wise +2.06
To make blur effect on UIImage iphone Problem? 0.00
Can I program the LUT5_D in virtex-5 FPGA with 2bit 2-to-1 mux func... -0.06
VHDL: Problem with unexpected IF +0.44
How to read in a bunch of strings in C++? +1.36
How does one find non-conformance to a spec when both the RTL'ers a... +0.44
How to initiate BRAMs with image data 0.00
convert integer to std_logic -0.39
how to test simulation results for 256 point FFT written in verilog... 0.00
Provide input data to FPGA using USB -0.07
How to find out which version of Synplify you're using in a tcl scr... -0.06
Is initialization necessary? +0.06
How to know if HW/SW codesign will be useful for a specific applica... -0.07
VHDL and using the 'report' Statement -0.53
VHDL integer'image Returns "0" -0.11
Running time vary on Microblaze after code modification 0.00
Tool to Monitor Serial Port in USRP2 0.00
Sharing (including?) generics in VHDL between files? -0.59
VHDL complement counter issues: converting std_logic to integer 0.00
Error during Netlist Generation in Simulink 0.00
4 FIFO and serialization 0.00
I'm using cudaMallocPitch and cudaMemcpy2D in CUDA but I dont get c... 0.00
Shift Right And Shift Left (SLL/SRL) +0.44
How to optimize an image processing class +0.40
Integer to Binary Conversion in Simulink +0.17
Nested if (rising_edge(clk)) statements in VHDL +0.41
Creating a frequency divider in VHDL -0.06
Where to declare a constant or type used in an entity declaration? -0.58
Signed division with unsigned numerator -1.78
Pattern Matching in Simulink 0.00
Stack overflow exception handling xe166 0.00
how to count 4us with the clock of 8MHz in VHDL? 0.00
VHDL generic parameters for entities -0.54
High Pass Filter for image processing in python by using scipy/numpy +0.19
VHDL entity and architecture design +0.46
How to obtain the maximum of a number in Simulink? 0.00
Implementing ceil function in Xilinx 0.00
Using Slice Block in Simulink 0.00
VHDL TG68 core data_in and data_out to datainout 0.00
How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL? -2.68
Timing Signal understanding in Xilinx Simulink +3.47
Encoding state machines in VHDL -0.32
Matrix Multiplication of two Complex Vectors in Simulink 0.00