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Answers and rating deltas for
Experiences with Test Driven Development (TDD) for logic (chip) design in Verilog or VHDL
| Author | Votes | Δ |
|---|---|---|
| Martin Thompson | 14 | +4.06 |
| toolic | 4 | +2.78 |
| bradheintz | 3 | +1.70 |
| Philippe Faes | 2 | -0.33 |
| Brian Carlton | 2 | -0.28 |
| Eli Bendersky | 1 | -0.46 |
| danielpoe | 1 | -3.48 |
Last visited: Sep 14, 2014, 5:07:29 AM