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Rating Stats for

Brian Carlton

Rating
1442.02 (4,534,231st)

Reputation
5,639 (29,108th)

Page: 1 2

Title	Δ
How do I list all Versions in Redmine	-3.42
Reasonable compression block-size	0.00
http://bi/ It works! What kind of domain name is this?	+0.14
Nested if (rising_edge(clk)) statements in VHDL	+0.75
using always@* \| meaning and drawbacks	-3.33
why is the output of `du` often so different from `du -b`	-3.43
Tool for helping with deduplication of Perl code?	0.00
Is there a VHDL equivalent to Verilog's @(*), i.e., automatic proce...	-2.77
How to sent message to the NIC of our own computer?	0.00
List files that are in directory1 but NOT in directory2 and vice ve...	+0.07
Emulate git cp, including files with spaces in names	-3.11
Tracker for UI bugs	-3.37
Tool to find commented out VHDL code	-3.48
Disk IO, performance issues with two files?	-3.44
FPGA Load Balancing stack	+0.38
Reading OUT ports for debugging	+0.54
how much for Sound (ADC) reading in 24khz?	0.00
Configuration Management for FPGA Designs	-0.09
Algorithms FPGAs dominate CPUs on	-3.54
include floating point library in vhdl	-3.66
Should you remove all warnings in your Verilog or VHDL design? Why...	+1.75
Should a developer be a coauthor to a paper presented about the app...	+0.33
How do I get rid of sensitivity list warning when synthesizing Veri...	+1.77
Make: how to continue after a command fails?	+3.02
How do I delete the first line in a file?	-1.84
Is hardware impossible to debug without software?	-1.21
Starting an application in OS X with low priority	+4.76
Online Perforce Repositories	-2.16
How to NOT use while() loops in verilog (for synthesis)?	-1.58
verilog modelsim fpga	-3.70
Perforce auto resolve (on a pending changelist) from the command li...	-3.70
Neural Network simulator in FPGA?	+0.23
How do online port checkers work?	-1.96
Best practices for TDD and reporting	-1.64
regex problem - select results by id	+1.99
Open-Source Field-Programmable Gate Array (FPGA) Development Tools	-0.70
Reviving a deleted file for use in my workspace	-2.16
FPGA Programming and how does IP Core licensing work?	-2.45
How do I rename a branch specification in perforce?	-3.73
Accurate Timings with Oscilloscopes on PC	0.00
Is it better to rewrite inherited code than fix it?	-0.18
Have you ever restricted yourself to using a subset of language fea...	-3.26
Is there a list of famous software products that do and do not do t...	-2.82
Best practice approach for automated testing	+0.80
Best resource for learning and seeing examples of Behavior Driven D...	0.00
Verilog: Can you put "assign" statements within always@ o...	-3.96
Experiences with Test Driven Development (TDD) for logic (chip) des...	-0.28
What are your Perforce practices for view/branches?	-3.74
Is there a product development model for an stand alone embedded pr...	-3.38
Tool for drawing timing diagrams	+1.32