StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

user1155120

Rating
1545.02 (9,583rd)

Reputation
12,280 (11,961st)

Page: 1 2 3 4 ... 13

Title	Δ
Parameterized constants in VHDL	0.00
vhdl can't slice records	-2.20
vhdl program for ripple carry adder showing warning about component...	+2.08
in test bench of SRFF terminal showing error " ; is expected i...	0.00
Error: Libero SoC 11.9 VHDL compile "A homograph of hread is a...	0.00
How to divide a vector by two in VHDL using 2 complement?	0.00
VHDL/GHDL Binary 32-bit Write Overflow When High Bit Set	+2.07
How to read text file line by line in vhdl by clk?	+1.80
VHDL Loops - Only last increment is done	0.00
Reading text length in Vivado	-0.18
fpga can't get simple register output	0.00
How to instantiate multiple components with variable size ports in...	0.00
no function declarations for operator	-0.19
Use of Array Slices in VHDL	+0.44
FIFO using vhdl	0.00
Creating a 16-bit ALU from 16 1-bit ALUs (Structural code)	0.00
sequential execution in process statement in vhdl	+1.86
Error (10028): Can't resolve multiple constant drivers for net...	0.00
Declare a variable number of signals with variable bitwidth in VHDL...	+0.44
How to create a subsignal / subvariable from an entity variable in...	-2.17
VHDL Column selection from array	-2.40
VHDL: Using aggregate others to assign value to more than one data...	0.00
vhdl expression has 2 elements, but must have 3 elements	0.00
Evaluate Assert First when Simulating	+1.13
Returning a generic width std_logic_vector filled with 0s to output	0.00
Use generate statement to create 'n' array of registers in...	0.00
Is there any difference if I remove NS from sensitivity list?	+0.44
Proper way of defining a type to hold sum of two integer in VHDL	+2.02
vhdl function is not being called	0.00
Adding two bit_vector in VHDL return error "(vcom-1581) No fea...	-0.56
VHDL Data Flow description of Gray Code Incrementer	-0.24
ISim shows U for all flip flops outputs	0.00
What is wrong with this vhdl code for bcd addition?	0.00
vhdl case...is and with...select	0.00
Replace code segment by text file content in VHDL	0.00
Using configuration specification in VHDL/ModelSim	0.00
procedure in VHDL returns unknown	0.00
Concatenating STD_LOGIC to STD_LOGIC_VECTOR within testbench in VHDL	+0.44
VHDL 2008 calculate length of vector without leading zeros	+1.86
Generating sine using cordic algorithm	0.00
Does anyone know why this VHDL code is not compiling?	0.00
How to use "function" in VHDL to return multiple variable...	0.00
VHDL: assign new value to the specific element of 2D Array	+2.04
This design contains one or more registers/latches that are directl...	0.00
How to include vhdl fixed point library to ghdl-0.33?	0.00
VDHL sfixed decoding code does not work properly	+2.05
How to concatenate two arrays in VHDL	+2.07
write on invalid address to RAM in VHDL, Verilog, sim behaviour	-0.08
How to create a pseudo-random sequence with a 16 bit LFSR	0.00
Array Parameterization in Module's Ports	-0.05