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Rating Stats for

Tim

Rating
1575.75 (3,409th)

Reputation
31,130 (3,869th)

Page: 1 2 3 ... 15

Title	Δ
How do I debug Verilog code where simulation functions as intended,...	-0.45
Error count for two different patterns in verilog	-0.19
Using Non-zero indexed Memory in Quartus (Verilog)	+0.39
Verilog Testbench Clock	0.00
Verilog counter counts wrong	0.00
Generating a reset signal	-0.61
Nexys3 interface to a VmodTFT	0.00
verilog asynchronous FIFO Wizard	0.00
Identifier must be declared with a port mode: busy. (Verilog)	-0.21
I'm new to verilog and please help me figure out what might be...	+0.46
Outputting a bitstream onto a pin in verilog	0.00
Behavioral algorithms (GCD) in Verilog - possible?	0.00
Systemverilog dynamic casting issues	0.00
Verilog Arithmetic Equation System Exercise	0.00
Verilog Image Filter	0.00
Verilog ISE compiler error: syntax error near if statement	0.00
Split up a four-digit number in verilog	0.00
Single Port Block RAM in verilog - spartan 6	0.00
How to generate a rising edge to control a shift register in verilo...	0.00
Verilog: ALU gives wrong output	+0.38
4-Bit verilog adder not passing carry bit	0.00
Strange component in quartus RTL viewer using verilog	-0.60
Using switches to change frequency of square wave in Verilog	-0.11
How to treat useless outputs in Verilog?	0.00
Rotate left verilog case	+1.71
Cannot evaluate genvar conditional expression	0.00
How can I insert text behind the specified character in Vim?	-0.02
Parallel multiplier-accumulator based on radix-4 Modified booth alg...	0.00
synthesize-xst in xillinx get a long time	-2.45
Verilog two-way handshaking example	+1.01
How to find MAX or MIN in Verilog coding?	-0.62
Verilog: Passing parameters	+0.39
hdl verilog Compiler Errors	0.00
event.getAction() never use MotionEvent.ACTION_UP	0.00
Icarus produces different results than Silos	0.00
Module 2D array passing	0.00
verilog doesn't see my function	+0.40
Pipelined design issues with Verilog	0.00
Verilog Base 2 Clock Divider	0.00
instantiating a module inside an always block	+0.39
Verilog runtime error and ModelSim	+0.37
Always block not behaving as expected	+0.39
Simulated Verilog Outputing all X's.. I've been very careful with R...	+0.38
Share hash across Perl scripts	+0.18
shifting bits of input in verilog	0.00
Expecting an identifier	0.00
Structural Verilog) creating a mod-12 counter with 4 D-FF - no outp...	0.00
Verilog: trying to blink leds in series using a clock divider at mu...	0.00
BCD to Excess 3 verilog code (case)	0.00
Verilog macro expansion	0.00