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Answers and rating deltas for
Simulated Verilog Outputing all X's.. I've been very careful with Reg vs Wires
| Author | Votes | Δ |
|---|---|---|
| Tim | 2 | +0.38 |
| Vineeth VS | 1 | +1.60 |
| DOS | 0 | -2.16 |
| alex.forencich | 0 | -2.48 |
Last visited: Sep 14, 2014, 5:07:29 AM