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toolic

Rating
1621.40 (1,065th)

Reputation
35,458 (3,239th)

Page: 1 ... 8 9 10 11 12 ... 23

Title	Δ
Running tshark in perl script	0.00
Using Perl how to read in a file and parse through logs to find err...	+1.13
how to check valid file in windows using perl?	-0.11
Array reference versus scalar reference	+1.15
Format specifications for real numbers	0.00
How do i get the input and output names of Verilog module using scr...	+1.86
Argument "*" isn't numeric in array element	+1.92
Always loop Verilog	0.00
Getops error in option spec	0.00
Error: Inconsistent with 'net' object	0.00
How can I filter the latest occurring filename from a certain direc...	+1.71
Adding and Subtracting values in Verilog	0.00
a simple increment register	0.00
Perl loop through hash of arrays	0.00
strange thing in concatenation verilog	0.00
Perl command to generate str of lower case, upper case and numbers	0.00
Perlcritic: How can I resolve '^Magic variable "$ENV"...	-0.84
red output running testbench on 4bit ALU	0.00
What is the wrong with this verilog code?	0.00
selective data transfer in verilog	0.00
Verilog FSM controller and datapath	0.00
Perl Tie::File - Get 5 lines from a file into an array while removi...	-1.66
Incorrect (?) delay results in modelsim (Verilog)	-0.12
file/Multi-channel descriptor (2) passed to $fclose in not valid	0.00
replication operator for ignoring bit	0.00
Is there a way to get the name a Verilog module was instantiated wi...	0.00
Verilog testbench	0.00
Perl - Error "Type of arg 1 to each must be hash (not hash ele...	+2.66
Perl check if elements is contained in array	-0.59
Perl String comparison	+0.19
Verilog: Initializing value from other file?	0.00
Unable to understand the behaviour of Perl hash ordering	+0.53
perl: split one column into two	0.00
How do I create a set from a multi-line string in Perl?	+0.40
Perl Reference, how is the passing a count variable($#) get the ref...	-0.43
how to change the value of parameter in verilog	-0.31
Elevator in Verilog	0.00
Passing parameters to Verilog modules	0.00
Perl: how to do math operations within a command?	+0.10
Verilog: Check, if a signal is 100 ticks active?	0.00
extracting substring with regex in perl	+1.59
ERROR: HDLCompiler:806 ... Syntax error near "end"	0.00
Insert string or comment into vcd dump file	-0.09
nested while loops in Perl	+0.40
Verilog testbench code using gEDA and iVerilog	0.00
Ring Oscillator Verilog code	0.00
vcd not generating with right format	0.00
How to obtain the complement intervals from an array of intervals i...	+0.93
Pass only one location of ram to another module in verilog	0.00
comparing t_data and rx_data for errors and giving the error value...	0.00