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Answers and rating deltas for
Incorrect (?) delay results in modelsim (Verilog)
| Author | Votes | Δ |
|---|---|---|
| Greg | 0 | +0.07 |
| toolic | 0 | -0.12 |
| Eugene Sh. | 0 | +0.41 |
Last visited: Jan 1, 2016, 11:45:33 PM