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toolic

Rating
1621.40 (1,065th)

Reputation
35,458 (3,239th)

Page: 1 2 3 4 ... 23

Title	Δ
PISO register output is not as expected	0.00
Searching a file name using regex and glob variable	+0.51
Invalid module instantiation	0.00
How to print an array in a matrix format	+2.00
$display not working properly in testbench	0.00
Cannot load/store data from/in SRAM: read data is unknown	0.00
High impedance for output, and undefined output and input for repla...	0.00
Verilog conditional assign outputs X where there should be 1	0.00
D FlipFlop sequence generator for the sequence 1101011 does not gen...	0.00
Problem with reset Johson Counter Verilog	0.00
Johnson Counter Syntax error. Unexpected token: generate	+0.33
sign extender in Verilog giving don't cares?	0.00
Store and read string with newline from Config::Simple config file	+0.32
Unable to create directory using make_path	0.00
Flip flop testbench shows incorrect values	+1.64
Verilog counter always block is not working	+0.33
Port size (8) does not match connection size (4) for port 'A'	0.00
Why does iverilog generate a syntax error for always_ff?	0.00
How to grep undefined values in an array?	-2.14
Output from a counter not showing as initialized in Verilog simulat...	0.00
Outputs always X using assign statement for creating bcs	0.00
How to fix the "Illegal reference to memory A" error	0.00
JK Flip-flop using D Flip-flop and gate level simulation does not s...	0.00
ROM 4kx8 verilog, problem with reading file with $readmemb	0.00
Verilog garbage input does not result in garbage output	0.00
Verilog Synthesis Error (Synth 8-151): Case item is unreachable	0.00
What is "concurrent assignment to a non-net <port_name>...	0.00
How to write to a hash with map without over-writing hash?	-1.50
Error: ordered port connections cannot be mixed with named port con...	-0.68
Error: (vsim-3033) Ripple_counter.v(22): Instantiation of 'JK_f...	0.00
bit-wise negation in systemVerilog	0.00
Replacing a hash with a variable when calling a function	-0.18
How to remove the repeated consecutive elements in dynamic array in...	-0.60
Seven Segment Display outputs are unknown	0.00
Using implication operator for different address ranges	0.00
Why do I get this error: Illegal operation for constant expression?	0.00
Verilog testbench error multiplex 4x1 using EDAPlayground	0.00
Verilog compile error: Unidentified variable 2'b00	0.00
Warning:Instantiation depth... This might indicate a recursive inst...	0.00
How do I fix Syntax error near "=" in casez statement?	0.00
How do I resolve Verilog simulation error: "Too many port conn...	0.00
vivado simulation error: Iteration limit 10000 is reached	0.00
How to write a behavioral level code for 2to4 decoder in verilog?	-2.75
The output does not change synchronously on Moore circuit design	0.00
How do I build a 5-bit maximal-length Galois LFSR in Verilog?	0.00
Passing parameters between modules in Verilog	0.00
Verilog bitwise XOR on 1-bit signal	0.00
Perl : Regular Expression with changing decimal to hexadecimal	+1.67
How to separate the Hex 8 bits into two 4 bits	+1.52
How can I make each module instance read from a unique file?	0.00