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Rating Stats for

Karan Shah

Rating
1435.95 (4,534,948th)

Reputation
1,248 (128,185th)

Page: 1 2 3

Title	Δ
Using function inside constriant block	-1.21
Do synthesis results differ between packed and unpacked arrays in S...	-1.24
ignore coverage bin of one instance of covergroup	+0.08
How to check signal unknown pulse width larger than specific value...	0.00
Systemverilog modport access to interface clk without being declare...	0.00
Is there a way to access uvm_phase from the testbench top?	+0.59
What is the best way to check an event occurred in the past in SVA?	+0.34
How to make such a clock counter in Verilog HDL?	-0.16
Can you use/manipulate same output/reg variable in multiple always...	-0.77
How to more easily make coverpoints for each bit in a bus?	-1.19
Taking the top 64 bits from a multiplication in verilog	-0.80
uvm_component parent in the class constructor	+0.25
how to use assertoff from test to disable assertion in side uvm obj...	+1.52
Difference between {a,b} == 2'b10 and a & ~b in verilog	-1.21
assume() does not work for initial statement	-0.41
Change the top level's variables inside the called modules in v...	+0.68
assimilating values to registers in GCD FSM in verilog	+0.23
Parameterizable cross length	-2.83
how to implement verilog divisible by 6?	-2.92
In Verilog, counting and outputting the number of 1's in an 8bi...	-2.49
Concatenate signal names in systemverilog using macro	-2.52
Verilog - If Condition	+4.76
Trying to assign an 18 input switch into six 3-bit variables in Ver...	+1.50
How does #delay work for verilog non blocking statements?	-3.69
set and get queue values using uvm_config_db	0.00
Multiple clock generation [Verilog] [Using fork-join]	-3.74
Verilog Falling Edge Detection	-3.61
Concatenating elements of unpacked array together	-1.66
How to synchronize two unrelated UVM sequence items from different...	+4.53
What is the purpose of UVM Virtual Sequencers	0.00
System Verilog randomize address equal to 2 to the power off	+2.88
Sampling covergroup of parameter array - systemverilog	0.00
What are the common and good usage of pre_randomize() and post_rand...	-2.97
SystemVerilog Constraint, Fixing value every nth iteration	-2.63
systemverilog return dynamic array from function	0.00
T-flip flop in Verilog	0.00
Can a SystemVerilog function return a value of a type defined in a...	0.00
Force all X's to be 0	+0.45
Why have negative-valued signed literals?	-2.67
Can I cross reference named module instances in SystemVerilog?	-2.70
Difference between different UVM packing	0.00
what is the purpose #(10) in verilog instance?	0.00
SystemVerilog assertion	0.00
adapter for sequence to use different bus drivers	+0.46
is there an alternative to non-blocking assignment in verilog?	0.00
Coverage done by monitor or subscriber in UVM	0.00
Error using for loop [procedural assignment to a non-register i is...	-1.28
Negative of a number in verilog using 2's complement	+0.39
Specifying the Rise and Fall Time for clocks	0.00
$past with an input signal	0.00