StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

CliffordVienna

Rating
1513.74 (49,692nd)

Reputation
5,589 (29,382nd)

Page: 1 2 3

Title	Δ
How to use 'write_json' command in YosysJS	0.00
Lattice iCE40 JTAG	0.00
Reset behavior with miter equivalence checking	0.00
How to output dependency files in Yosys (gcc -MMD equivalent)?	0.00
ICE40 up5k Internal internal oscilator and ip's	0.00
Manual manipulation of verilog connections	0.00
(icestorm) do pins not specified in the pcf stay high impedance	0.00
What are yosys formal capabilities with verific?	0.00
How to run post-synthesis simulation with the IceStorm iCE40 FPGA f...	0.00
how to decompose a circuit into high-level modules	0.00
Yosys optimizes away ring oscillator on ice40 FPGA	0.00
How can I use multiple IP cores that both contain modules with the...	0.00
Can I avoid opt_merge from removing a BUF? (Yosys tri-state workaro...	0.00
Yosys gives syntax error on 2d interface	0.00
Yosys logic loop falsely detected	+0.48
Primitives in Yosys	0.00
How to assign RAM values in an initial block in Yosys?	0.00
Parameters to Script	0.00
Is it possible to remove clock input variable from the AIGER output?	0.00
Constraints(Time/area..) in Yosys and/or ABC	0.00
timing issues: simulation (iverilog, gtkwave) works, hardware (yosy...	0.00
required size of a configuration file for a HX1K (in "SPI slav...	0.00
Extending existing cell libraries	0.00
Superfluous buffers/inverters in synthesised netlist	0.00
Can we have variables in a Yosys script?	0.00
Understanding the bitstream generated for iCE40 I/O tiles	0.00
Correspondence between iCE40 I/O blocks and package pins	0.00
Analyzing bitstreams using Icestorm	0.00
yosys rtlil dumps incomplete	-0.02
Why is this MUX with const. inputs not optimised away?	0.00
How do I get multi-bit ports to work in Yosys when the module is BL...	0.00
Combinatorial synthesis: Better technology mapping results	0.00
How to map clock gate to tech library cell	0.00
How can I use iCE40 4K block RAM in 512x8 read mode with IceStorm?	0.00
Some questions about wires with private name in Yosys	0.00
Why does yosys renumber vector ports?	0.00
How to put a list of cells into a submodule in yosys	0.00
How to create Gate Level Verilog from higher level Verilog using yo...	0.00
How do I use set LVDS mode on Lattice ICE40 pins using ICESTORM tools	0.00
Conditional compilation in ice40_synth using yosys?	0.00
Yosys FSM Detection State Assignments?	0.00
Executing get-model or unsat-core depending on solver's decision	-2.67
iCEstick + yosys - using the Global Set/Reset (GSR)	0.00
What are the useful attributes that can be used with passes in Yosys?	0.00
iCE40 IceStorm FPGA Flow: Bi-directional IO pins	0.00
Yosys how to use the qwp command	0.00
How to perform Depth First Search (DFS) inside a module starting fr...	+3.86
How to get the AST result as a textfile from YOSYS	0.00
RISCV VERILOG HDL code	+3.91
Synthesizable Verilog modular shift register	0.00