StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Jack Koenig

Rating
1503.96 (251,869th)

Reputation
2,673 (63,199th)

Page: 1 2 3

Title	Δ
Reg of Vec of Valid(Vec	0.00
How the mask can be used in aggregate memory in chisel?	0.00
when-otherwise Statement vs. Mux Statement	0.00
Chisel: getting signal name in final Verilog	0.00
Use chisel to implement a relatively large-scale project, how to ch...	0.00
How to to use the val name of selected element in a chisel Vector i...	0.00
Extending Data Types or way to add information	0.00
Why does sbt fail with "Expected ';'"?	-1.90
Creating Modules in chisel dynamically and at the same time passing...	-1.75
Chisel3: Vec indexWhere expected Bool, actual Any	0.00
How to test modules with bundle/vec input?	+2.27
How to soft reset Chisel Counter	0.00
Most frequent value in a dataset in scala	-1.93
systemverilog union type in chisel	0.00
How to use uint to do bit extraction	0.00
How to use this built-in shiftRegister from Chisel3.util properly?	0.00
How to extend chisel3's bundle to a specific width the value th...	0.00
Testing of a RegisterFile in Chisel	0.00
Is there any way to use chisel to generate blackbox from verilog te...	0.00
Is there an accepted way to get a Gray Code counter in Chisel?	+0.37
How do I make an individual Rocket tile asynchronous to the rest of...	0.00
Designing a filter using scala - For loop unrolling	0.00
How to avoid re-downloading the sbt dependency package when moving...	0.00
Is it possible to have a while loop in chisel based on a condition...	-1.76
How to pass a operator as a parameter	-1.78
Chisel variable Declaration Syntax Meaning rvs: Bool*	0.00
How do I write to a conditional output	-0.25
Possible workaround for async negedge reset?	+0.49
Got an unnexpected error: "Attempted reassignment of binding t...	0.00
Chisel randomly initialize register value when simulating with veri...	0.00
How to keep val names under withClock() or withClockAndReset() scopes	0.00
Is there a way to make signals in Chisel not defined at module scop...	0.00
How to initialize a Reg of Bundle in Chisel?	+0.56
Chisel compiled successfully but can't generate correctly verilog	0.00
How to split an UInt() into a Vec of UInt to do subword extraction...	0.00
How to express specified index range of a Vec?	-0.03
Maintain connection order on FIRRTL using Cat operator	-0.50
How to use Seq with Cat in Chisel?	+0.47
value is not a member of chisel3.Bundle	0.00
"for-loop" to reduce coding on Chisel3.2	+0.56
Expression _GEN_7 is used as a FEMALE but can only be used as a MALE	0.00
can you synthesize RSICV rocket chip testharness module?	0.00
How to generate code to RTL with blackbox?	0.00
sbt could not find implicit value for parameter valName	-0.11
chisel-firrtl combinational loop handling	0.00
What is the purpose of the makeSink method in making IOs for a peri...	0.00
declaration and Variable scope in chisel and When block	0.00
Is there a way to warn wrong clock domain crossing in Chisel3?	0.00
How to use a chisel3.experimental.ChiselEnum in an I/O port?	-2.35
How to keep all variable name In chisel when generate Verilog code	0.00