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Rating Stats for

dave_59

Rating
1560.31 (5,540th)

Reputation
21,379 (6,248th)

Page: 1 ... 24 25 26 27

Title	Δ
How to monitor DUT outputs from a test/sequence?	+3.68
SystemVerilog better way to copy a class	0.00
virtual interface in system verilog also dynamic array cannot be us...	+3.98
Inheritance-like feature for interfaces	+3.83
Register virtual class with UVM factory	0.00
System Verilog: enum inside interface	-4.14
Constraints for arrays in system verilog	+3.55
how to write function about return data	0.00
Must use non-blocking assignment in a procedural block in System Ve...	0.00
Handing reset in SystemVerilog assertions	+4.29
Interface System verilog with a verilog module	0.00
passing a class as data between synthesized and unsynthesized modul...	+3.73
How does a system verilog structure be realized in hardware? are th...	+3.82
Does UVM support nested/inner classes?	+3.88
Set multiple registers in a single line (Verilog)	0.00
Practical use of fork join_none	-3.36
Contradiction in IEEE 1800-2009 LRM wrt `timescale	0.00
nonblocking statements and fork-join in verilog and/or system verilog	0.00
Using parameterized aggregate datatype in ANSI-style module port list	0.00
Is it possible to create SystemVerilog wrappers with modports for V...	0.00
UVM RAL: Randomizing registers in a register model	0.00
How do I compare two signals whose edges are almost in the same pla...	-3.62
Does ModelSim support program blocks?	+4.45
Systemverilog assignment - logic array to byte array	0.00
need concept to understand declaration of array in system verilog	+3.85
system verilog - uvm - wait for pkt in sequence	-0.05
How do form Variable names by using defines in system verilog	+4.10
calling $dumpvars() from a task	+0.79
How can I create a task which drives an output across time without...	0.00
UVM: Does setting values to sequence_item before I call start_item(...	0.00
How to intercept uvm_error and cause a callback?	0.00
Modeling z on a real in system verilog	0.00
Class object print in system verilog	0.00
What SystemVerilog features should be avoided in synthesis?	0.00
Verilog - generate weighted random numbers	+0.96
Difference between scoreboard and checker	+4.16
Integration of VIP developed in VMM into my UVM testbench	0.00
How to parameter MUX using SystemVerilog	-1.50
Strategy to share signals between predefined UVCs	+0.54
Defining an array in verilog down to a nonzero constant	-3.35
randamization in system verilog	-0.02
How to randomize contents of a very large memory?	+0.42
UVM Phase Query	0.00
Enable On Function/Method Call	0.00
UVM: illegal combination of driver and procedural assignment warning	0.00
How do we declare multi-bit registers in verilog?	+4.31
How do I stop all running sequences in UVM?	0.00
Why is output not driven through interface clocking block?	0.00
Object reference count in System Verilog	-3.49
do system verilog parameters reduce simulation speed	-3.57