StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

dave_59

Rating
1560.31 (5,540th)

Reputation
21,379 (6,248th)

Page: 1 ... 23 24 25 26 27

Title	Δ
Quartus and modelsim - compile size casting	-0.18
How factory is implemented inside UVM?	0.00
Inheritance & Virtual Interface in systemverilog?	0.00
What is the meaning of an object of the class inside it's class...	0.00
Which region are continuous assignments and primitive instantiation...	0.00
Using Systemverilog static variable in class	0.00
Insert string or comment into vcd dump file	+0.05
Array of systemverilog interfaces with different inputs	+0.43
multi bit clock converged to single bit using type casting	0.00
Reading wrong data when indexing a nested array	0.00
Is there a system task or pre-processor directive in SystemVerilog...	+3.44
define visibility in system verilog	0.00
I am trying to code a 8-bit,4x1 multiplexer and I have seen some wh...	0.00
How to test the current instance name?	+3.45
how to nor two vectors in dataflow verilog?	-4.60
how to get rid of tr_db.log in uvm-1.2?	-4.34
Concatenation operator in System verilog in a loop	-4.50
Program & Clocking Block Rules in System Verilog	0.00
What is need of Assign/Deassign in Verilog?	+3.44
Can Verilog/Systemverilog/VHDL be considered actor oriented program...	-4.55
How can I make Modelsim exit with a specified exit code from System...	+3.38
SystemVerilog error 10748	+3.58
How do you initialize uvm_mem?	0.00
System verilog:: Static Variable non-blocking Assignent outside pro...	+3.54
Setting multiple values in a vector to a single value	-4.04
Calling ModelSim commands from SystemVerilog	+3.49
Defining interface inside a package	0.00
Accessing SystemVerilog code during simulation	+3.82
Error loading .a files in questasim	0.00
Undefined global variable when using QuestaSim	0.00
Why delays cannot be synthesized in verilog?	-0.33
Printing packed structs in System Verilog	-3.19
How to test primality in Verilog?	0.00
Getting the hierarchical scope from where a function was called	0.00
Constraining an entire object in SystemVerilog	-0.05
Parametrized uvm_events for uvm_sequence	0.00
SystemVerilog mixing non blocking and blocking assignment for arbiter	+3.51
System Verilog Clocking block	-0.40
uvm_field_* macros - how do I set my custom struct	+3.52
What is the standard methodology of verifying HW when there are cas...	+3.52
$readmemh to load subblocks of memory	0.00
Passing string values to SystemVerilog parameter	+4.13
Verilog module order	+1.81
How to properly cast arrays in SystemVerilog?	+3.67
system verilog interface for multiple clocks	0.00
When to use the tick(') for Verilog array initialization?	-3.83
SystemVerilog foreach syntax for looping through lower dimension of...	-3.02
Is Reading of a clocking block output in system verilog is allowed?	0.00
Failing to write in systemverilog mailbox	0.00
Clock skew assertion	0.00