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Rating Stats for

Chick Markley

Rating
1553.05 (7,102nd)

Reputation
1,560 (105,281st)

Page: 1 2 3

Title	Δ
Chisel Passing Enum type as IO	0.00
Symbol 'type <none>.experimental.MultiIOModule' is mi...	0.00
Chisel: How to change module parameters from command line?	-0.08
How to Split a State Machine in multiple Classes or Traits in Chisel?	0.00
How to exchange certain bits of the register	0.00
Poking individual bits using peekpoketester	0.00
How to create ROM with VecInit(Array()) in Chisel?	0.00
Is it possible to declare conditionnal signals in io bundle?	0.00
Dumping memory in a VCD file	0.00
How to freely assign values to vec type variables in chisel？	0.00
Get an item in Seq using UInt	0.00
How to integrate my testbench in chisel with a C++ library?	0.00
How to convert a deprecated low Firrtl Transform to the Dependency...	0.00
Retrieving chisel source description inside of treadle	0.00
Creating IO bundles using dynamic parameters in chisel using MixedVec	0.00
Chisel3 REPL Vec assignment into module only works after eval	-2.00
Chisel3 REPL Vec assignment into module only works after eval	+2.00
Creating Modules in chisel dynamically and at the same time passing...	+1.75
How to create a array/vec of Chisel modules	0.00
Fixed point number representation in FIRRTL	0.00
Printing UInt and SInt values in CHISEL	0.00
Chisel3 REPL peek value is correct but expect fails in test	0.00
How to test modules with bundle/vec input?	-1.61
Simple chisel dual port memory Read port issue	0.00
Module is an object or a class?	0.00
Timing of expect() @Chisel3 Tester	0.00
Is there an accepted way to get a Gray Code counter in Chisel?	+0.08
What does this Chisel exception mean: Caused by: chisel3.package$Re...	0.00
Is it possible to have a while loop in chisel based on a condition...	+1.76
How to pass a operator as a parameter	+1.78
Generating waveforms with ChiselTest framework	0.00
How to dynamically add IO ports to a Chisel Bundle?	0.00
How to generate a random Scala Int in Chisel code?	0.00
In Chisel3, what imports do I need for the Printable examples?	0.00
Can chisel implement printf to a file?	0.00
How is this syntax explained in chisel?	+3.72
Why this chisel code compiling without error with wrong size UInt a...	0.00
Chisel test - internal signals	0.00
Chisel bootcamp 3.2 Muxes result wrong?	0.00
How to add include path of verilog to blackbox in chisel (3.2)	0.00
Inner product (Dot product .) between two signal 4 bits using Chisel3	0.00
How to initialize a Reg of Bundle in Chisel?	-3.12
Chisel Synchronization	0.00
How to reinterpret IO signal when testing chisel3 modules	+3.51
Question regarding lazy evaluation for Diplomacy (rocket-chip)?	0.00
Developer's guide for Chisel?	0.00
How to make Data Structure	0.00
Error while passing values using peekpoketester	+3.48
How to convert from Uint to Int	+1.54
Can't poke MixedVec	0.00