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Rating Stats for

Hadi Brais

Rating
1545.33 (9,460th) 		Reputation
10,771 (13,997th)
Page: 1 2 3 ... 7
Title Δ
Why “movnti” followed by an “sfence” guarantees persistent ordering？ 0.00
Failed to reproduce the high-precision time measuring kernel module... 0.00
PMC to count if software prefetch hit L1 cache 0.00
AMD: performance counter for cycles on TLB miss 0.00
On x86-64, is the “movnti” or "movntdq" instruction atomi... 0.00
How does kernel know physical memory base address? +1.76
Is clflush or clflushopt atomic when system crash？ +2.26
GCC inclusion of AVX512's "Fused Multiply Add" instru... 0.00
Let perf use certain performance counters properly with newer proce... 0.00
How does DC PMM (memory mode) cache coherence behave? 0.00
Are snoop requests sent to all the cores in a multi node setup? 0.00
Problem with the information displayed by the cpuid command -2.20
How do I see how many slices are in the last level cache? 0.00
Profiling Cache hit rate of a function of C program -0.60
How to generate a zero-length read on PCIE Bus using x86-64 and Lin... 0.00
Does clwb take care of the write in store buffer? 0.00
Perf shows L1-dcache-load-misses in a block with no memory access 0.00
Width of bus betwen cpu cache and cpu 0.00
Am I correctly reasoning about cache performance? 0.00
RISC-V instruction to write dirty cache line to next level of cache 0.00
Does cmpxchg write destination cache line on failure? If not, is it... +1.64
In which cases GetSystemInfo/GetLogicalProcessorInformationEx retur... 0.00
Can constant non-invariant tsc change frequency across cpu states? 0.00
Are X86 atomic RMW instructions wait free +1.68
Get x86 SMEP CPU flag from user mode 0.00
Why are there too many demand rfo offcore responses /offcore reques... +0.26
Why is LOCK a full barrier on x86? 0.00
Intel's CLWB instruction invalidating cache lines 0.00
What resource_stall.other might mean 0.00
What happens to expected memory semantics (such as read after write... +0.70
How does Linux kernel flush_write_buffers() work on x86? +2.36
Distinguishing volatile vs persistent variable, does it affect corr... 0.00
How does the indexing of the Ice Lake's 48KiB L1 data cache work? -0.54
Loop takes less than 1 cycle despite dependency between iterations 0.00
IA32 vs MSR prefix for x86 MSR names 0.00
Does Cache empty itself if idle for a long time? +0.46
Branch Predictor Entries Invalidation upon program finishes? -0.40
What does sys_schedule() do in Minix 3.1.8? -0.05
Why do newer Intel CPUs not suppert performance counter for stalled... -0.54
Storing a general purpose register in st0 0.00
Understanding TLB from CPUID results on Intel 0.00
Does the running of a second thread on an hyperthreaded CPU introdu... +2.31
Uses of the monitor/mwait instructions +1.81
What do the different fields in PERF_RECORD_SAMPLE mean? 0.00
How to use perf_event_open under sampling mode to read the value of... +1.86
x86 Program Counter abstracted from microarchitecture? -0.94
What is the meaning of IB read, IB write, OB read and OB write. The... 0.00
What IARG_EXPLICIT_MEMORY_EA should be used for? 0.00
How to correctly determine -march and -mtune for Intel processors? +2.55
Temporal locality in memory mountain 0.00