StackRating

An Elo-based rating system for Stack Overflow
Home   |   About   |   Stats and Analysis   |   Get a Badge
Rating Stats for

Hadi Brais

Rating
1545.33 (9,460th) 		Reputation
10,771 (13,997th)
Page: 1 2 3 4 5 ... 7
Title Δ
Does clflush also remove TLB entries? -0.93
Throughput analysis on memory copy benchmark +1.92
Why jnz requires 2 cycles to complete in an inner loop +2.44
Performance analysis of CPUs for parallel executions 0.00
(How) can I predict the runtime of a code snippet using LLVM Machin... 0.00
Weird performance effects from nearby dependent stores in a pointer... 0.00
What's the difference between conflict and compulsory cache miss? 0.00
Why LRU implementation is expensive in full associative TLB? 0.00
What's the purpose of castclass opcode in CLR? 0.00
In which condition DCU prefetcher start prefetching? +2.40
Are write-combining buffers used for normal writes to WB memory reg... 0.00
When profiling in Release build mode, is the generated code really... 0.00
Why does the call latency on clock_gettime(CLOCK_REALTIME, ..) vary... +2.44
Cachegrind: Why so many cache misses? +2.21
Does volatile prevent introduced reads or writes? -0.38
How to make sure to avoid branch misprediction when calling a metho... +0.49
How does an implementation of the c sharp specification ensure stat... +2.48
Are all micro-ops the same length in a modern x86 CPU? 0.00
What is cpumask in mm_struct 0.00
Quantitative metrics for parallelism 0.00
How many bits there are in a TLB ASID tag for Intel processors? And... 0.00
Performance and scalability of applications in parallel computers 0.00
Committed Vs Retired instruction 0.00
Is it possible for the RESOURCE_STALLS.RS event to occur even when... 0.00
Why does the number of uops per iteration increase with the stride... -1.55
weird addresses in stack buffer overflow article -0.01
Do prefetch instructions need to return their result before they re... 0.00
Is there a penalty when base+offset is in a different page than the... -1.55
What is "Interrupt" for transition of a process from runn... 0.00
What is "the kernel address space"? 0.00
Copying a bool from a parameter to a global - comparing compilers o... -1.57
why perf has such high context-switches? -1.70
Pipeline on Registers calcuation +1.60
Is it valid to write below ESP? -1.75
Choice between aligned vs. unaligned x86 SIMD instructions +1.99
Memory latency measurement with time stamp counter +0.48
Can the LSD issue uOPs from the next iteration of the detected loop? 0.00
Understanding the impact of lfence on a loop with two long dependen... -0.27
Xeon CPU (E5-2603) backward memory prefetch 0.00
Memory Models and Concurrency +1.51
Is LFENCE serializing on AMD processors? -0.49
Why did Intel change the static branch prediction mechanism over th... +0.02
clflush to invalidate cache line via C function +0.42
Performance difference between two seemingly equivalent assembly co... 0.00
Exclusive access to L1 cacheline on x86? -1.61
perf mem error event 'cpu/mem-stores/P' not supported 0.00
Does a hyper-threaded core share MMU and TLB? 0.00
What is the relationship between the _mm_sfence intrinsic and a SFE... 0.00
Can loads slip beneath an acquire operation / can stores float abov... 0.00
Will adding more memory slices increase the overall memory bandwidth? 0.00