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Rating Stats for

Hadi Brais

Rating
1545.33 (9,460th) 		Reputation
10,771 (13,997th)
Page: 1 2 3 4 5 6 ... 7
Title Δ
How can I create a spectre gadget in practice? 0.00
Is there a way to determine that SMM interrupt has occured? 0.00
Is Core Affinity Something that We Can Safely Do in .NET? -0.40
Intel Pin: correctly continuing execution after RECEIVED_ACCESS_FAU... 0.00
Difference between far JMP and far CALL in a long 64-bit mode 0.00
Intel Pin: measuring empty instrumentation overhead 0.00
Globally Invisible load instructions -1.63
Is there any other OS project out there? 0.00
why is the physical address of a mmap value is aways zero? 0.00
What does "serializing operation" mean in the sfence docu... +2.39
Is this requivalent to the ret instruction? 0.00
Can I not use release and acquire barriers in this case? -1.61
Why does p1007r0 std::assume_aligned remove the need for epilogue? -1.66
Workaround for Spectre warning MSVC C5040 +1.42
What data structure is typically used to implement a frame table? 0.00
What is vmovdqu doing here? -1.29
How virtualized page table works +0.19
How linux kernel knows the address passed as argument in syscall is... 0.00
Where is the lock for a std::atomic? -1.80
Do locked instructions provide a barrier between weakly-ordered acc... +1.88
Who performs the TLB shootdown? -1.46
MIPS pipeline registers length (IF/ID, ID/EX, EX/MEM, MEM/WB) 0.00
Just as in Segmentation, can different addresses in Paging also poi... +0.31
Do modern CPU's have compression instructions -0.87
How to use _PAGE_BIT_SOFTW1? 0.00
Skylake and newer Ring Bus 0.00
What is the benefit of the MOESI cache coherency protocol over MESI? +0.30
When are logical addresses created? -0.64
Where is the Write-Combining Buffer located? x86 +2.31
how to interpret perf iTLB-loads,iTLB-load-misses 0.00
Can subsequent writes be reordered when one of the variables is con... 0.00
How many and what size cycles will be needed to perform longword tr... 0.00
Why is the RX ring of a Linux raw socket limited to 4GB in size? 0.00
Does MSVC 2017 support automatic CPU dispatch? 0.00
Address translation with multiple pagesize-specific TLBs 0.00
Stack limit and recursive functions 0.00
How does an OS "deal in" virtual addresses and physical a... +0.28
Why segmentation cannot be completely disable? 0.00
Is there any case where the Bimodal will be better than Not take? 0.00
C# Shared Memory - risk of CPU caching (non-volatile reads)? 0.00
Passing arguments to own execv kernel implementation 0.00
Are there any Operating Systems that use non preemptive scheduling... +1.40
Logical address space non-contiguous or Physical address space non-... 0.00
Can exec*'s argv contain a value of 0 in multiple places? 0.00
What does 0 flag mean in shmflg for shared V memory system calls? 0.00
How does Linux kernel migrate the process among multiple cores? 0.00
Do (sampling) profilers still "lie" these days? +1.01
Can Multiprocessor CPUs avoid context-switching? 0.00
Why not just predict both branches? 0.00
Out-of-order execution vs. speculative execution +2.34