StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Jonathan Drolet

Rating
1550.32 (7,843rd)

Reputation
2,857 (59,149th)

Page: 1 2 3

Title	Δ
VHDL: convert "real" and "time" variables into...	0.00
VHDL Clock problem while creating modulo 16 counter	0.00
Generating Huffman Tables for Motion JPEG on FPGA	0.00
Self implemented UART in VHDL always skips second character	0.00
Xilinx Floating Point Core - Erroneous 'X' values?	0.00
Why is the mod operator not defined for real values?	0.00
VHDL - Synthesis	-0.08
Fixed Point Multiplication for FFT	0.00
VHDL what does this mean? a <= a (6 downto 0) & '0'	+0.43
write integer to file vhdl	0.00
How do I set a Port to Ground using Vivado's I/O Planning tool	0.00
Value assignment inside if block in a VHDL process not working	0.00
Directly Instansiating a DSP Slice Without IP Core	0.00
Xilinx Virtex II Pro - Determine Number of gates	0.00
VHDL newbie errors i cannot understand	0.00
XILINX ISE set I/O Marker as Clock	0.00
Can I read/write from the same buffer while also using a triple fra...	0.00
Reusing an old component in VHDL	0.00
Video conversion from 720p to 480p JPEG - FPGA	0.00
VHDL : 'X' value in result of Adder	0.00
modification in UCF file in Xilinx xps	0.00
Dividing a constant by an std_logic_vector	0.00
How to get rid of scale factor from CORDIC	+3.82
Warning about getting "X"es for 4-valued logic VHDL	0.00
how to add two 16-bit STD_LOGIC_VECTOR and a carry into 17-bit in V...	0.00
Booth Multiplication Algorithm	0.00
Power and timing reports of two different vhdl designs	0.00
Generic vhdl design with multiple drivers	0.00
Reset output after run	+3.69
VHDL modulo 2^32 addition	0.00
DMA PCIe read transfer from PC to FPGA	0.00
Expression out of bounds on MATLAB with HDL coder app	0.00
LATCH Primitive disables outputs?	0.00
Query on VHDL generics in packages	-4.37
VHDL: Convert String to Std_Logic_Vector	0.00
Convert binary ( integer and fraction) from VHDL to decimal, negati...	-0.70
How to set value of a signal for AXI GPIO	0.00
Convolution by Dirac Delta on Xlinx FPGA	0.00
Dynamic Arrray Size in VHDL	+3.12
VHDL. The signal value isn't changed after new value assigning	+3.41
RAM to read/write in VHDL	0.00
AXI4 (Lite) Narrow Burst vs. Unaligned Burst Clarification/Compatib...	0.00
Behavioral into FlipFlop Structural	0.00
VHDL My timer don't work	-0.27
rising_edge(clk) not synthesizable	-2.83
How to activate a timer on sdk?	0.00
Creating a tachometer in VDHL	0.00
how to implement FPGA coprocessing with C/C++ on zynq 7020?	+3.54
Gated clock warning	-0.26
4-bit Shift register with flip flop	0.00