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Rating Stats for

JHBonarius

Rating
1499.54 (3,776,328th)

Reputation
3,612 (46,560th)

Page: 1 2 3 4 5 6 ... 7

Title	Δ
Forming an array from items in list of lists	-0.80
Thrust+boost code compilation error	+0.48
const method modifies object using reference	-1.32
Read Python data into C++ code	0.00
System Generator error: "The inputs to this block cannot all b...	-0.02
Difference between BIT_VECTOR and ARRAY OF BIT	0.00
Cast (C like) pointer to C++ matrix	-0.71
Please help me with VHDL compile error	0.00
What is labels used for in VHDL?	+1.99
compiling in GPU using thrust (prime numbers)	0.00
Istream operator overloading '>>' cause infinite loop	0.00
I want to assign a switch (SW) to an input (D)	0.00
Creating std::set copies only one element, how to fix this?	0.00
C++ Smart Pointers erroring	0.00
c++ Make pointer point to another inside a function	-0.53
C++ Boost binary serialization of std::map conatining pointers cons...	0.00
C++ Boost binary serialization of pointer constructed from Boost ob...	+2.60
Interface DHT22 to FPGA - elbert v2	0.00
Conditional element replacement using cellfun	-1.62
Too many values to unpack in lambda function	0.00
two's complement binary VHDL	0.00
How to find frequency of a clock divider ?	0.00
use datas introduced in the same line C++	-0.27
C++ Insert result of permutations into a vector	-1.75
FFTW producing different results from numpy.fft	+0.48
sequential execution in process statement in vhdl	-1.86
Variable generic assignment in generate loop	0.00
VHDL: Unable to assign anything to Integer array Output Port	0.00
How do I instantiate parameterized versions of generic designs in V...	0.00
Implementations of an Adder in VHDL comparison	0.00
Is it correct to state that the first number that collide in single...	+1.32
How to create a subsignal / subvariable from an entity variable in...	+2.17
With Modelsim .do file, how to compile a list of files using vcom	-0.50
Referencing entity generic inside package in VHDL?	0.00
Arithmetic operations in vhdl. How to multiply std_logic vector by...	+0.23
VHDL use input value at clock edge	0.00
ostream operator << in Namespace hides other ostream::operator	0.00
Reading binary file in vhdl	+2.44
VHDL Error: TwosCompliment.vhd(16): near "process": expec...	-0.01
VHDL shift_left/shift_right stopped working	+0.48
VHDL ignores statement outside a process	-0.52
in VHDL, how to assign list of output ports to an array?	0.00
Translating a VHDL code to Verilog	0.00
VHDL Warnings that my outputs are not connected to any drivers	0.00
VHDL No Delta Delay Input to Output Assignment	-0.02
Evaluate Assert First when Simulating	-0.67
Explain the math behind progressively reaching a target position	-1.13
Access range of specific elements of std_logic_vector in one clock	-1.60
Error (10327): can't determine definition of operator "&qu...	0.00
How to resolve "Register/latch pins with no clock driven by ro...	0.00