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Rating Stats for

JHBonarius

Rating
1499.54 (3,776,328th)

Reputation
3,612 (46,560th)

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Title	Δ
VHDL Condition in if must be static and component instantiation ins...	0.00
Array aggregation on self-defined types?	0.00
Error compiling VHDL in VLSI	0.00
Simulating VHDL 2008 unconstrained array type in Vivado 2017.1	0.00
VHDL- Pseudo Random Number Generating with Seed using linear equati...	0.00
asking help for vhdl error	0.00
How can I undo something set in the global modelsim.ini?	+1.79
Calculation of var in R	+0.41
VHDL generic case statement	0.00
Do input and output ports behave like flip-flops? (VHDL)	-0.45
Resetting Preg of Dsp slice in virtex 6 FPGA	0.00
VHDL NxM -bit parallel block multiplier	0.00
Assigning Records VHDL	0.00
Sed + RegEx to delete comments from VHDL file	-0.52
Testbench of SR Fliflop in VHDL	+0.73
i don't understand the utility of default values in state machine	0.00
CUDA 9.0 and pycuda, error:CompileError: nvcc compilation ... kerne...	0.00
VHDL typecast signed to std_logic_vector	0.00
VHDL 2008 calculate length of vector without leading zeros	-1.86
Shift Register or FIFO in block RAM (Xilinx)	0.00
VHDL: Using array of std_logic vs. using subtype of std_logic_vector	0.00
VHDL 3-bit sequence counter with T-Flip Flops	0.00
problems writing to an avalon slave module	0.00
AWGN channel in VHDL testbench	0.00
Why is this not synthesizable? (does not hold its value under NOT(c...	+0.22
How to send a floating point number to FPGA from HPS?	0.00
(ARCHITECTURE pcarch OF ENTITY program_counter) : Error : Type mism...	0.00
How to decode fixed point (VHDL) number in HPS using c language?	0.00
How i can read this ram and return a q = 1 when two addresses have...	0.00
How to count pressed keys on FPGA spartan board	0.00
compare modelsim simulation result with a theory text file using vhdl	0.00
VHDL ERROR : Can't resolve multiple constant drivers for net......	+0.49
How to get singed integer in HPS from value of signed std_logic_vec...	0.00
Modelsim "Failed to map the library" error	0.00
Slice even/odd elements in VHDL	-0.24
VHDL wrapper for 1-wire core for DS18B20 temperature sensor	0.00
How to calculate sin inverse (arcsin) in VHDL?	-4.16
How to use sin, arcsin functions in vhdl Quatus 2 16.1 Lite?	0.00
Function clogb2() generated by vivado can't synthesize with loo...	+4.10
Confusion in VHDL code	0.00
Modelsim: Does a 'X' in a std_logic_vector affect the other...	0.00
VHDL up/down counter error counting	0.00
Synthesis (Top Level Function Warnings)	0.00
How to count pixels using AXI Stream signals?	0.00
VHDL enumeration with specific bit length	0.00
Running post-synthesis in Xilinx ISE	-0.17
Finite state machine VHDL reset	0.00
Receiving data from RS232, vhdl	0.00
Warnings XST1293 and XST1896 during synthesis	0.00
using internal ADC in spartan 3e 1600e fpga kit	0.00