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Rating Stats for

Russell

Rating
1504.18 (176,279th)

Reputation
2,453 (68,773rd)

Page: 1 2 3

Title	Δ
VHDL - Inferred Latch With Reset - FSM	+0.50
Pause/Stop AjaxDataSource Bokeh Stream	0.00
How to force a single bit in an array of bits in systemverilog?	+0.25
Convert from signed to unsigned in VHDL properly	-0.51
VHDL shift_right number	+2.26
Vhdl How to make a simple addtion of binary with fixed point?	0.00
Is this a look ahead adder? And how to benchmark it?	0.00
Is it possible to turn the clock off in vhdl?	-0.47
how to dump signals inside a task or function	-1.50
MSP430 UART TX Interrupt Enabling/Disabling	0.00
How to allocate contiguous memory for dynamic multidimensional arra...	+0.25
Why can't I declare a shared variable in the same package as th...	0.00
VHDL multiple std_logic_vector to one large std_logic_vector	+0.52
How to make the library work work?	+1.33
Issue formatting "if" statement within testbench process?	0.00
Error while testing Assert statement in Xilinx	0.00
Error: <signal> is not a constant	0.00
How to change slew constraint for a port from slow to fast?	-0.55
How to generate an asynchronous reset verilog always blocks with ch...	0.00
Why DCM doesn't work in Modelsim 10.3?	0.00
i2c comunication in vhdl, an X bit when going form master ack to fi...	-0.92
Matlab hamming to vhdl 8-bit	0.00
How to pipeline my 2s complement multiplier?	+0.01
VHDL code for turning 50MHz into 38KHz	+0.49
Signal assignment in VHDL? Critical Warnings	0.00
Compilation errors in Verilog	-1.77
Hardware interpretation in verilog for blocking assignments	0.00
Query : No display on monitor ( VGA CONTROLLER 800*600 resolution )...	0.00
2 Bit Counter using JK Flip Flop in Verilog	+0.23
Verilog: Concatenation with unsized literal, but why?	-1.77
Verilog: Converting BCD (or binary) to BCH	0.00
vhdl programming scale the value from 32 scale to 100 scale	+2.38
Read binary file data in Verilog into 2D Array	+0.50
Trying to show one cycle of 8 bit LFSR with VHDL	0.00
Verilog Tri-State Issue (Xilinx Spartan 6)	0.00
Generic driven customizable bus width on port of symbol	0.00
Shift register uses too many logic elements	+4.20
Uart Vhdl, simulation is ok but in fpga not work	+0.03
Variable and constants in VHDL	+0.84
DSP unit usage in VHDL	-3.41
Using a for loop inside a clocked process: "Cannot generate lo...	-2.03
Illegal type conversion VHDL	-3.97
Syntax error near "posedge"	0.00
Port Mapping memory components not working	+4.13
VDHL: when else clause inside case clause	0.00
Adding Even Parity bit and 2 stop bits to a 8 bits std_logic_vector	+4.07
How can I assign something to nothing in Verilog?	+4.21
VHDL error please	+0.07
Adding Library to VHDL Project	+0.19
Testbench in VHDL	+0.85