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Rating Stats for

Morgan

Rating
1511.40 (62,220th)

Reputation
15,904 (8,804th)

Page: 1 ... 7 8 9 10

Title	Δ
Conditional instantiation of verilog module	+0.72
Seven Segment Multiplexing on Basys2	-4.14
Counter With Frequency divider is not incrementing	+4.46
SVA (SystemVerilog Assertions) : Difference between $assertoff and...	0.00
verilog parameter as input - nios II	+0.39
Use of wire inside an always block?	0.00
Ripple Counter Using Dflip flop	+4.52
Implement FIR Filter in Verilog	+0.07
verilog : defining parameter values in case statement?	0.00
Subscript indices must either be real positive integers or logicals...	-0.33
Illegal reference Error	0.00
Which Version of Matlab introduced isrow and iscolumn functions?	0.00
verilog output is delay by 1 clock cycle	0.00
verilog to FSM convert	-1.92
Plots created by figure function in just one window	0.00
What is "gate count" in synthesis result and how to calcu...	0.00
How to access text files at synthesis level	+0.25
Incisive Formal Verifier Installation 64 bit	0.00
how to map reg values to the ports of other module	0.00
Verilog Mealy FSM with 1 module	0.00
How can I create a latch in Verilog	-1.51
In Verilog, how to "hold" the value of the rest of a regi...	0.00
How to make the 2-complement of a number without using adder	-3.31
How to implement a (pseudo) hardware random number generator	0.00
Concatenation in Verilog seemingly not using full width	+3.93
Sign of expression in Verilog	0.00
verilog counter implementation unexpected behaviour	-4.06
How to choose a random number within a given time?	+0.28
Compiler modifications for new hardware	-0.17
How to create a new database with ActiveRecord in a non-rails app?	+4.04
How to declare input and output types in verilog	+3.95
Why use this 2 DFF method every time a button press is involved?	0.00
Verilog HDL Negate Monitor Variable	0.00
does this 16 bit carry look ahead adder looks correct in structual...	0.00
$display every time $monitor works in Verilog	0.00
how to go about designing a 16 bit carry look ahead adder in verilog	0.00
Timing issue in Verilog	+0.04
Generate random number - seed changes only once	+0.74
Splitting a bit array in Verilog	+4.14
Define a 2D array in verilog, a 4x4 matrix that storage specific va...	0.00
$size, $bits, verilog	+3.99
Verilog 'for'-loop returned values	0.00
How to require files by default without mentioning explicitly	+4.34
Difference of SystemVerilog data types (reg, logic, bits)	0.00
zero flag in verilog problems	+0.18
Two's complement in verilog	0.00
Verilog contention with next signal	0.00
How to make multiple wires quickly in Verilog?	+4.93
Using '<=' operator in verilog	+0.91
How to emulate $display using Verilog Macros?	-3.59