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Rating Stats for

Morgan

Rating
1511.40 (62,220th)

Reputation
15,904 (8,804th)

Page: 1 ... 5 6 7 8 9 10

Title	Δ
Verilog multiple drivers	-0.03
Multiplication, multiply register verilog	0.00
Instantiation of a generic module in Verilog	0.00
grouping of bits in square root division	0.00
verilog average, add n-bit numbers together and then divide by nbit...	0.00
Generics in hardware description language	-0.27
How to generate delay in verilog using Counter for Synthesis and ca...	0.00
Using case statement and if-else at the same time?	+0.30
iterative read data from more than one files in verilog	0.00
Multiple if condition with single else in verilog	0.00
Assigning entire array in verilog	+0.49
Verilog - generate weighted random numbers	+0.30
Verilog, handshakes and clock rates	0.00
Verilog state machine based on switch inputs and button presses	0.00
Verilog: How to instantiate a module	0.00
If statements causing latch inference in Verilog?	-0.52
How to convert Signed Binary to Integer in Verilog?	0.00
Why put delays in Verilog even for some simple assignment?	-0.25
Sequential Division verilog	+0.49
Comparing integer and binary in VHDL	+0.22
Flip flop with load/set, reset, clk, and input	-0.02
Verilog branch instruction MIPS	-0.51
Instantiating a value in or out of an always block	0.00
What does #`DEL mean in verilog?	-0.01
Verilog: task using case not choosing the correct case	0.00
Include a module in verilog	0.00
system verilog assertion trigger==1 4 cycles before signal asserted	+2.20
How to synthesize a block of registers as ROM in verilog	+0.49
Synthesizable code to save the output in a file in verilog	0.00
Design a decoder with unknown number of inputs using verilog	0.00
the inputs must be registered and then magnitude must be taken of 2...	0.00
Verilog: how to take the absolute value	-0.01
Verilog disable Statement not Working but $finish works but it is n...	+0.04
For-loop in Verilog	+0.27
Verilog bitwise or ("\|") monadic	+0.50
Verilog : Use of 'PARAMETER during instantiation	0.00
Is there a code editor plugin for chrome?	+0.49
I understand the fundamentals of verilog, but test bench just won't...	-0.51
what's the difference in position declaring variable in xilinx?	0.00
How to Synthesize While Loop in Verilog?	-0.24
Rounding off a number in verilog	-0.01
How do I specify weak feedback inverter in Verilog	0.00
How to design a variable bit (m bit) counter using VHDL or Verilog?	-2.02
Verilog code adding two integers generated by a for loop	0.00
How do I instantiate two modules with one module in Verilog?	0.00
Shifting a Concatenate Register	0.00
Verilog Loop Condition	-0.32
Low power design for adders	0.00
How to enable the instantiated modules in sequence in verilog	0.00
What division algorithm should be used for dividing small integers...	-0.00