StackRating

An Elo-based rating system for Stack Overflow
Home   |   About   |   Stats and Analysis   |   Get a Badge
Rating Stats for

user1155120

Rating
1545.02 (9,583rd) 		Reputation
12,280 (11,961st)
Page: 1 ... 8 9 10 11 12 13
Title Δ
Directly indexing a bit of an arithmetic result 0.00
VHDL syntax error near while 0.00
')' expected. - VHDL 0.00
Subtractor Module VHDL generating wrong values +0.50
Synthesizable wait statement in VHDL 0.00
Shouldn't these types be closely related? 0.00
Is the VHDL package 'IEEE.std_logic_arith' shipped with ghdl? 0.00
Fill one row in 2D array outside the process (VHDL) -0.52
VHDL: std logic vector not holding value between process calls 0.00
How can i generate a pulse train to give output in common way? -0.02
VHDL adder, same word length? +0.41
What VHDL libraries to use for decimal modulus +0.50
How to get simulation warning when comparing std_logic with 'X&... +0.01
Type Error in VHDL +0.47
My function does not return a value, and I do not understand why? V... +0.50
Is this "glitch safe" clock mux really glitch safe? -0.53
What does "others=>'0'" mean in an assignment... +0.49
Address of array provided as std_logic_vector -1.68
Can a constant expression ever be valid in a VHDL case statement? -0.49
VHDL: Signal cannot be synthersized, bad synchronous description 0.00
VHDL - Xilinx ISE crashing during synthesis 0.00
VHDL FSM not changing states 0.00
How to copy bits of signal in FLOAT to STD_LOGIC_VECTOR representat... 0.00
Programming Altera DE2 for displaying colors on LCM in VHDL 0.00
Reading .hex file in VHDL 0.00
Write the VHDL text file for a 6-bit adder using INTEGER types 0.00
Error (10818): Can't infer register for ... at ... because it d... 0.00
VHDL: ADC interfacing code doesn't work on the fpga kit, gives... -0.01
Error (10500): VHDL 0.00
VHDL: truth table in ieee std_logic library 0.00
Shift register uses too many logic elements -0.26
git-core has been made obsolete by the port git -0.48
usage of IF statement in VHDL 0.00
The code which i posted is I2s code | I'm having the same error... +0.01
Errore VHDL Quartus -0.85
i'm generating a sine wave using the lut 0.00
Persisting an output in comb logic block -0.14
fatal error in modelsim during simulation +0.33
single port ram with timming specifications 0.00
Having troubles with running FSM on Nexys2 0.00
Is there a way to print the values of a signal to a file from a mod... -0.85
Getting warning error in vhdl code +0.33
When should endfile be used, before or after reading? -0.21
Assign two signals from the same statement -0.10
Why is this assignment ambiguous? 0.00
Syntax of the full hierarchical names used in Xilinx UCF files 0.00
issue with vhdl structural coding 0.00
Error: Unknown formal identifier on Vhdl Testbench 0.00
Std_logic_vector adding function +0.32
Integer or not, in vhdl +0.47