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VHDL use library function in Generate 0.00
Is Wikipedia's example on FOLLOW() sets in LR(1) parsing wrong? 0.00
How to read a binary file entirely and quickly in Ada? +3.89
Is process in VHDL reentrant? +4.02
Never-ending synthesis with integer incrementation 0.00
Connecting STD_LOGIC_VECTOR in different ways (Barrel Shifter) - VHDL 0.00
VHDL if statement - strange value 0.00
VHDL - Scrolling Text on 7 segment Display +0.34
VHDL: is using inout port bad practise? 0.00
VHDL - Shifting an array of bytes 0.00
How to index a std_logic_vector by enumeration +4.13
Why does my VHDL code have latches? -0.17
Developing multi-use VHDL modules 0.00
Converting numbers in Ada +3.50
Convert Enum to Binary (via Integer or something similar) +2.98
VHDL syntax to drop multiplication remainder +0.06
VHDL - Why a delay of 1 clock period in simple counter +3.39
'Process Models' vs 'Data/Object Models' in MVC -2.06
VHDL expression is not constant -3.61
Design tips for synchronising signals through a VHDL pipeline +4.31
mixed VHDL & Verilog designs: which free simulation and/or synt... +2.21
Comparing unsigned, including metavalues, to a bit pattern 0.00
Implementing a P controller 0.00
What is the least positive integer with no reciprocal in typical fl... -4.16
ODDR2 usage found in auto-generated xilinx wrapper VHDL file -2.51
What should be allowed inside getters and setters? -0.14
Draw circle vhdl -0.15
Types unmatch VHDL code at Simulation on Modelsim, inspite of thoro... +4.02
How to compile the linux kernel with an obsolete option? 0.00
VHDL Integer overflow +0.64
How to represent Integer greater than integer'high +4.26
Definition of a generic record +3.78
VHDL Structural vs Behavioral 0.00
Defining a generic scalar-type package in Ada +3.81
How to to create include files in vhdl? +4.40
Holding an action in VHDL +3.65
How to get pass this synthesizing phase? 0.00
Interrupt handling with fpga in VHDL 0.00
How to deduce from synthesis report +0.26
Type Safe vs Static Typing? -3.77
generate a table with random elements -0.70
Clock input ignored while waveform simulation in VHDL? 0.00
Generating a 78MHz clock from a 100MHz base clock -3.84
gnatlink fails under new Ubuntu version +1.62
How to represent array literals in VHDL? -3.93
Programming a PWM in an Arduino Mega ATmega2560 micro-controller 0.00
Can I put a large Ada program in an embedded system? -4.27
BRAM_INIT in VHDL 0.00
What is the difference between Facade and Gateway design patterns? 0.00