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user_1818839

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1581.09 (2,927th)

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Title	Δ
Variable initialization in vhdl	0.00
Issues with indexing arrays in VHDL	-0.01
Can custom types be used in port declaration?	0.00
Bug with the PHP exec() function for an ADA program	-0.34
How to write an array to text file ?VHDL code	0.00
Record containing access to instantiation of generic package based...	+0.37
VHDL code for converting floating point to fixed point?	+0.42
Warning: Design contains 1 high-fanout nets. A fanout number of 100...	0.00
Getting wrong results in post synthesis simulation	0.00
Infinite amount of time when trying to synthesize behavioral VHDL c...	-0.10
Initializing memory in netlist VHDL	0.00
Top module VHDL with no inputs and outputs	0.00
Conversion from Systemc to VHDL or VERILOG	0.00
Ada equivalent of local static variable from C/C++	0.00
Run multiple processes in VHDL	-0.29
Concurrent If Statements in VHDL	0.00
What does `&` operator do to a standard logic vector?	0.00
discrete cosine transform using VHDL	-0.10
Power function in vhdl	+0.41
How to change the range of the range type?	+0.39
VHDL synthesis of registers - separate process for each register vs...	-0.59
Making mp3 decoder VHDL code synthesizable	0.00
Synthesis warning in VHDL multiplier code	0.00
Avoid duplicating code in VHDL	0.00
VHDL Synthesis - FF/Latch Constant Value	+0.42
How to find zombies in Ada?	+0.39
Generating Single Port ROM on Spartan 6 using Xilinx ISE Design Suite	+0.40
VHDL RAM port map	0.00
cannot generate code for file	+0.38
VHDL library for basic elements	+0.41
How to use more than one delay counter in same process in VHDL	-0.09
Ada loop on number of type float untill it reach zero	+2.12
Programming Arduino with Ada	-0.00
Ada tasks and termination	0.00
VHDL Syntax error in IF-ELSE block of finite state machine	-0.07
ada 95 Put (Item : in String) vs Put (String)	0.00
fpga communication with pc	0.00
Can't resolve multiple constant drivers VHDL Error	+0.16
VHDL error related to Choises	+0.41
Vhdl Type mismatch error	+0.42
Program Exit with Status 255 C++ Main with Ada	+0.39
Error : Non-static loop limit exceeded	+1.07
VHDL Simple code optimization	-1.45
How can I make this VHDL code synthesizable?	0.00
Vhdl code acting wierd (small code , where variable keeps its value...	+0.42
vhdl: convert vector to string	-0.07
Is it possible to have generic type in vhdl?	+0.42
Is a <= a + 1 a good practice in VHDL?	+0.69
If there exists two component of same name, one in package and othe...	0.00
VHDL std_logic_vector indexing with "downto"	+0.06