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user_1818839

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1581.09 (2,927th) 		Reputation
15,299 (9,181st)
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Title Δ
UART RS-232 Transmitter +2.00
Signals and synthesis of registers/flip flops in VHDL 0.00
while loop in ADA83 -0.74
please help me, don't read the file "mem.dat" 0.00
Keep gettting an error with array(control memory, vhdl) +0.41
vhdl code for single octave digital piano 0.00
rising_edge function avoids "latch warnings"? +1.21
My sorting algorithm runtime errors +0.12
Pointers In C and other languages +1.20
Assign a single bit from STD_LOGIC_VECTOR to STD_LOGIC 0.00
what should i do with that vhdl design? 0.00
VHDL test bench error please help, for school (SOLVED) +0.43
How to read a Excel file in Ada? -0.60
VHDL nested conversions +0.40
What does a >> 1 mean? +0.25
VHDL invert if to reduce nesting +0.83
Driving module output from combinatorial block -2.00
reading the value of input when clk ='1' in the mid way of clk 0.00
VHDL ERROR:Pack:2811 - Directed packing was unable to obey the user... 0.00
VHDL Code Help -Break integer into pieces -0.24
Having several processes with the same sensitivity list 0.00
Override record fields 0.00
(VHDL) How to assign a summation result partially in one clock +1.60
syntax/logic errors in port map +0.01
Is there anyway to pass a type or subtype into and out of a function +0.59
What means CS and CSMap? 0.00
Compiling aflex in linux mint 64 bit 0.00
vhdl code (while loop) +0.39
vhdl code (for loop) +0.41
VHDL - variable vs. signal behaviour in queue +0.02
vhdl how to use an entity within a process 0.00
VHDL - How do you connect 1 output-bit to several 1-bit signals? -0.24
Connecting ports by name in VHDL, UCF-style -0.39
Type mismatch error in VHDL? 0.00
Ada types size difference +2.25
7 Segment Display with VHDL 0.00
Is it possible to synthesize VHDL code with variable in it -0.50
Evaluating exponential function in VHDL 0.00
VHDL 2D array of integer 0.00
Can't finish compiling a process with while loop 0.00
Not displaying waveforms in simulation without errors +0.20
Compilation errors - non-visible declaration at a-textio.ads 0.00
VHDL - FSM Control -0.31
Ada - Empty file -0.58
if and elsif optimisation in Ada 95 -0.85
Integer to String goes wrong in Synthesis (Width Mismatch) 0.00
Distribution in Ada +0.41
How to Transfer Array Data in VHDL? +0.16
Data Transfer between two Spartan 3E +0.48
Why won't this VHDL counter count +0.21