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user_1818839

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1581.09 (2,927th)
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Title Δ
Xst:647 Warnings during Synthesis of Shift6 with Top module +0.37
FPGA: Divide range by fixed number using a look-up table 0.00
How to stop execution in my program -2.04
CONSTRAINT_ERROR on reading a file containing "[" 0.00
Advanced computer architecture in HDL 0.00
VHDL is it valid syntax to use string in Generic? +0.37
How many Flip Flops will this code produce? 0.00
reading data into VHDL +1.51
Ada linker not letting me call my procedure 0.00
VHDL - FSM not starting (JUST in timing simulation) -0.14
Ada Program Hangs on Exception, gnatmake 0.00
Exception is not being caught with its name but it is caught when o... -1.70
For-loop in another for-loop VHDL 0.00
ISIM only simulates until 61.215.000 picoseconds 0.00
Can't manage to solve error ,VHDL, syntax error but I don't... +0.36
How expensive is data type conversion vs. bit array manipulation in... 0.00
Missing features of Ada record +1.56
VHDL short form to trigger actions on raising edges -0.36
compilation based on environment variables 0.00
Registers created for output ports in FSM, why? +1.61
Trying to use a buffer in VHDL - not working -0.40
No feasible entries for infix operator "=" [VHDL] -0.02
VHDL: How can I shorten a 32bit expression? +1.15
Why am I getting a "No matching subprogram was found." er... -0.11
Why is named association required for a one-element record aggregate? +0.39
VHDL: issues with adding and subtracting +1.62
VHDL VGA sync circuit +0.00
Ada + Fixed Stringss + Stm32 Arm -0.02
reset statement is not synthesizable since it does not hold its val... 0.00
Ada random numbers are identical -1.04
Is there a way to read WAV files off an SD card on a DE2-115 withou... 0.00
VHDL Coding .. conversion from integer to bit_vector +1.96
Simulation blinking LED using VHDL with Quartus II and ModelSim -0.11
Ada get Character input and check if it is a valid input 0.00
Is it possible to use a process inside a 'case is when' str... +0.95
VHDL: How to assign value to an input? +1.65
Can Ada functions return arrays? +2.28
VHDL Dynamic slicing using mathematical expression 0.00
how to make constant function in Ada? +2.03
undefined symbol: __gnat_rcheck_CE_Invalid_Data when linking ADA wi... 0.00
My inputs keep being ignored in VHDL +0.43
Ada concatenate Integer with String -1.51
Variable and constants in VHDL -0.11
String output strangeness 0.00
Getting warning error in vhdl code -0.33
Trouble having Implement Shift Operator (sll) in VHDL 0.00
vhdl function package test +0.42
Do I have to write the `else` statement when implementing a registe... -2.03
"near then expecting <= " what is this error? -0.08
IF syntax error in simple VHDL code +1.67