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1512.40 (55,550th)
15,499 (9,054th)
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Title Δ
How does cache coherence work when there are multiple levels of pri... 0.00
How to insert a new element in array in c -0.78
Efficiently accessing 2 array of structs in a loop 0.00
multiple locks on different elements of an array -0.57
Determine Cpu cache associativity 0.00
Hardware Multithreading and Simultaneous Multithreading(SMT) +0.48
Has Python got branch prediction? 0.00
Why is accessing every other cache line slower on x86, not matching... 0.00
OpenMP nested loop with dynamic array assignment -0.52
Avoid stalling pipeline by calculating conditional early -1.53
CPU spatial cache locality in array iteration +2.28
Emulate a very fast (virtual) CPU core +0.29
Is there a penalty for accesses to virtual addresses which are mapp... -2.14
Cache coherence- MESI protocol +0.32
Is it possible to compare ARM and x86 performance via benchmarks? 0.00
How to ensure that one instruction is finished before a second inst... -1.01
Trying to pass the output of echo into mkdir command +2.51
Cortex A53 L1 L2 caches info 0.00
When accessing memory, will the page table accessed/dirty bit be se... -0.03
Why can't a load bypass a value written by another thread on th... 0.00
Why cannot the load part of the atomic RMW instruction pass the ear... 0.00
In what case would a uniprocessor system invalidate it's cache? -0.38
Measure the number of lines loaded in l1/l2 cache for reads(includi... 0.00
How Can I Aware Register Spilling via Objdump File? 0.00
Why does malloc give different addresses on "b" and "... +2.27
Algorithm - find all permutations of string a in string b +1.94
Loop stride and cache line 0.00
CPU bound vs Cache bound - Can instructions be executed without cac... 0.00
Cannot understand the metric returned by "perf" regarding... +1.32
l2 cache CPU comparisions 0.00
Can't reproduce cpu cache-miss -0.51
MESI protocol. Write with cache miss, but cache line copy exists on... 0.00
Is Haswell dual path execution CPU? -1.85
According to Intel my cache should be 24-way associative though its... 0.00
Will a TLB miss in all scenarios point out whether a page is missin... 0.00
Why denormalized floats are so much slower than other floats, from... -0.01
Linked lists, arrays, and hardware memory caches 0.00
How does CLFLUSH work for an address that is not in cache yet? +1.98
Is semaphore needed for read/write access to a boolean +0.51
How did he split the bits in the physical address? 0.00
Identification registers in a processor 0.00
Intel compiler optimization +0.93
How to prevent two processess from fighting for a common cache? +0.49
Why is the total number of possible substrings of a string n^2? -0.55
Why does copying a 2D array column by column take longer than row b... -1.74
Why am I not a victim of branch prediction? +0.45
Associative Set Cache Underestimating Hit Rate 0.00
Do memory allocation functions indicate that the memory content is... +1.24
Stringification of int in C/C++ -0.90
Is there a neater way to do this? C++ IF +0.99