StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Peter Cordes

Rating
1575.42 (3,453rd)

Reputation
156,434 (349th)

Page: 1 ... 44 45 46 47 48 ... 92

Title	Δ
What does it mean to "train" a branch predictor?	+1.34
How do the shuffle/permute intrinsics work for 256 bit pd?	0.00
Instruction reordering on intel	+0.35
Why does this AT&T assembly code give a segmentation fault?	0.00
Open MP: SIMD compatible function in SIMD loops?	+1.33
Dividing with a negative number gives me an overflow in NASM	+0.43
Query about legacy 3DNow! instruction set	+2.11
Word length of computer	0.00
Optimal buffer size to avoid cache misses for recent i7 / i9 CPUs	0.00
Segmentation fault while moving value to stack pointer	0.00
movsb asm not working as expected	0.00
Which Intel microarchitecture introduced the ADC reg,0 single-uop s...	-0.45
C++ code execution time varies with small source change that should...	+0.65
Comparing Intel vs Arm Registers with Swift / lldb	0.00
x86_64 Dot Vector Product Intrinsic to ARM64	0.00
Make a register depend on another one without changing its value	0.00
reading volatile variable outside of scope of a mutex as opposed to...	0.00
how to compare 32 bit char against 32 bit char in, inline assembely...	+0.75
Achieve window function InterlockedExchange in Linux	0.00
Intriguing assembly for comparing std::optional of primitive types	-0.22
perf report shows this function "__memset_avx2_unaligned_erms&...	0.00
What considerations go into predicting latency for operations on mo...	0.00
achieve GCC cas function for version 4.1.2 and earlier	-0.37
Move single byte from memory to xmm register as float	0.00
How to use XACQUIRE, XRELEASE Hardware Lock Elision (HLE) prefix hi...	-0.45
Could multi-cpu access memory simultaneously in common home computer?	-0.82
Exclusive access to L1 cacheline on x86?	+1.61
Call a function in another object file without using PLT within a s...	+0.38
How to debug an "unresolved externals" error when trying...	0.00
Can you generate new asm files based on old ones? And if so what is...	0.00
Difference in data alignment in struct vs parameter?	0.00
How to tell length of an x86-64 instruction opcode using CPU itself?	0.00
How is this x86 assembly code receiving and storing the data return...	0.00
AT&T syntax hello world works but intel syntax does not	-1.65
How to define the length of a vector prior to using x86 SSE assembl...	0.00
ELF INIT section code to prepopulate objects used at runtime	-1.19
Why does the compiler reserve a little stack space but not the whol...	-0.61
x86 registers: MBR/MDR and instruction registers	0.00
spectre with device memory	0.00
Memory Protection Keys Memory Reordering	0.00
Which x86 instruction has a 10-byte immediate?	0.00
gcc arm inline assembler %e0 and %f0 operand modifiers for 16-byte...	0.00
Matrix transpose and population count	+0.38
Is there any architecture that uses the same register space for sca...	-0.33
Sharing memory with the kernel and compiler optimizations	0.00
Are lock-free atomics address-free in practice?	0.00
How to avoid the error of AVX2 when the matrix dimension isn't...	0.00
How to correctly measure IPC (Instructions per cycle) with perf	0.00
Using RSI/RDI vs r8-r15 (speed optimization)	0.00
How to set/clear TF flag on x86 IA32 Intel CPU in user-mode	+0.38