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dave_59

Rating
1560.31 (5,540th)

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21,379 (6,248th)

Page: 1 ... 7 8 9 10 11 ... 27

Title	Δ
Declaring and using a static array of constants	+0.37
is it possible to override uvm test that is specified via +UVM_TEST...	0.00
Connect different port width	+1.39
What counts as an illegal hierarchical reference for a virtual inte...	0.00
How to define a constraint for one bit random variable?	0.00
How does one describe signal concatenation with logic diagram blocks?	-0.48
Inter & Intra Delay Confusion with Blocking & NBA in Verilog	0.00
Why always block not reactivating when there is a reassignment of l...	0.00
randomizing number of 1's in an array in UVM without using $cou...	0.00
Extra iteration of while loop in System Verilog	0.00
Absolute value module in Verilog returning only unknown values	0.00
How to change verbosity of uvm components after certain condition	0.00
Automatically pad SystemVerilog packed structs so that they can be...	0.00
Variable slicing vector Systemverilog	0.00
Does enum literal deceleration of states guarantee a glitch free st...	-0.50
When I compile my Verilog code I get this message. Anybody know wha...	-2.53
Calling tasks from different testbenches systemverilog	0.00
Verilog if else structure	-0.64
How does this Verilog Code work? It has two separate but same neged...	-2.66
How to flag an issue in SystemVerilog spec	0.00
VHDL-2008 external names: reference verilog net?	0.00
Verilog: looping instances in hierarchical path	-0.67
Is it possible to use a type defined with "typedef enum"...	0.00
Trouble creating time delay in verilog	0.00
How to generate PWL or pulse in verilog without using clock	0.00
SystemVerilog covergroup include coverpoint based on parameter	0.00
Register spreadsheet to xml conversion	0.00
Defining generated clock as synchronous in RTL simulation	0.00
Can be a few supply1 nets in verilog code? If yes, what is the mean...	0.00
What does 'include and 'define means? and what do they do?	0.00
How to fix inferring latch(es) error when I use a for loop?	0.00
Verilog: assigning to a module input from within the module itself...	0.00
Default type input and output signals SystemVerilog	0.00
How to build an up-counter in Verilog	0.00
Distinguishing between local data member and child-class data membe...	0.00
Delay associated with xor of 1023 10 bit vectors in Verilog	0.00
Quartus 14.1 encrypted files used in Quartus 17.1	0.00
Polymorphism behavior	-0.69
Adding delay to the output in Verilog	-0.15
how to return assosciative arrays in system verilog	+1.53
Verilog - Is it possible to create two vcd files during the same si...	0.00
Systemverilog interfaces over hierarchical boundaries	0.00
atobin() and atohex() in systemverilog	+1.33
Verilog : A task with continuous assign output for local variables	-0.68
Verilog bit metadata	0.00
access two instances with same code without repeating it for each one	-0.69
Is it possible to create a enumerated data-type that consists of 2...	0.00
Concatenate block of memory into a wire array?	+0.36
Synopsys Synplify Pro synthesis failed when using "``"	0.00
SystemVerilog Interface data type with list of instance names	+0.36