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Oldfart

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System Verilog using mask -3.99
VHDL Cannot Drive Load pins +3.88
VHDL Filter not getting output for first values +0.06
Verilog code: initializing an 2D array using nested for loop 0.00
Delays within tasks in system verilog 0.00
How to fix Xst:528 this signal is connected to multiple drivers 0.00
Verilog 2's complement adder/subtraction +0.03
mixing of blocking and nonblocking issue and first bit of the 16-bi... 0.00
Specify default value to variables in verilog always 0.00
verilog output stuck on last if statement 0.00
Uart Module and op 0.00
Very new to verilog. Can't assign values in a loop +3.69
Two pointers in ROM hardware implementation 0.00
Can I reduce the number of bits after Arithmetic Right Shift? 0.00
my verilog code doesn't work 0.00
Converting from vhdl to verilog 0.00
sliding window in verilog when doing convolution 0.00
Gray code fifo getting number of elements in buffer -5.73
Shortests version to choose posedge/negedge sensitivity from module... +3.79
System Verilog Bus Routing +3.81
How to fix Xilinx Xst 1710 warning 0.00
the difference between x and z (Verilog) +3.74
Verilog Error in all assignings 0.00
4-bit Ripple Carry adder testbench in vivado +0.05
Implementation of Network on Chip on FPGA 0.00
$display not working {Verilog testbench) +0.05
Verilog ignores @(posedge sd_clk) delay 0.00
Is always block needed for a generate-instantiated module to propag... -4.04
Verilog ip core floating point calculations 0.00
Reading data in verilog 0.00
floating point random number generation in verilog. 0.00
how to do post synthesis simulation in vivado 0.00
X value on flop enable equation +0.04
Verilog - Assigning a value to high 0.00
how to properly connect receiver, sender and top and make them depe... 0.00
How to work with DDR in synthesizeable Verilog/VHDL? 0.00
Counter through Verilog +4.17
Unused sequential logic element removed. Unsure why it is unused 0.00
Creating Demux in Verilog 0.00
33 * 33 bit using 16 bit DSPs 0.00
Counting 0-9 with Verilog with Frequency Divided Clock for FPGA 0.00
How to have a binary number with constant lenght +5.10
Fast array inner access in verilog 0.00
Pipelining a verilog module consisting 10 components connected in s... 0.00
Verilog - Quartus compilation error after compiling FPGA Rom 0.00
ModelSim Verilog compiler error 0.00
How to generate random number of flops in system verilog? +4.04
ERROR: 'Checker 'xor_module_b' not found. Instantiation... 0.00
Verilog, Parallel in Series out Shift Register 0.00
Shifting transmit data to position of receive data in loopback mode 0.00