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Oldfart

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What is the difference b/w following two statements in verilog: 0.00
"Not a valid l-value" Error in Verilog 0.00
randomizing 32 bit value in systemverilog with xilinx vivado 2018.2 0.00
VHDL testbench for a device that uses two previously defined and te... -0.24
Fastest Way to Dynamically shift a 16 bit register 0.00
Always block - Do RHS signals in an assignment ,inside always block... 0.00
Will temp variable in always_comb create latch -0.02
Random real numbers with uniform distribution in verilog 0.00
VHDL core synthesis and implementation in Vivado -1.80
Values in counter written in Verilog cannot change and stay always... 0.00
Proper way to synchronize two state machines with slightly skewed c... 0.00
Index register with different widths 0.00
verilog code for ram 0.00
Can input port be of type reg in verilog? 0.00
synthesizable way to load initial values in verilog +0.01
How to control a single bit within a variable? +0.47
get MAX or MIN (signed) in Verilog? +0.50
Counter not working in FPGA 0.00
VHDL - connect switch and LED 0.00
Process doesn't work due simulation 0.00
Usage of a non blocking assignment in Verilog -1.76
How windows progran can transmit an input and get an output to an F... -0.01
Verilog Multiple Counters 0.00
Sequential element is unused and will be removed from module in viv... 0.00
Can clock edge events be synthesized inside always blocks in verilog? 0.00
VHDL Generic component declaration syntax error 0.00
Can you use/manipulate same output/reg variable in multiple always... +1.64
VHDL Error 10568 can't write to interface object "a"... 0.00
Giving inputs to error checking module from PRBS generator in verilog 0.00
Strange behaviour in VHDL -0.26
how to write to common register from two always block 0.00
What's the difference between Verilog Test Fixture and Verilog... 0.00
My Verilog output test results in a value of x 0.00
Differences between how a simulator and synthesizer treats VHDL code 0.00
Trouble with 8-bit Carry Lookahead Adder in Verilog 0.00
Assinging inout port to inout in both directions -1.51
What is the disadvantage of this approach to VHDL state machine des... 0.00
How to make ACLK centric data transfer 0.00
Verilog - Issue with Main Module for Adder 0.00
Signals not going forward from initial state in Verilog test bench 0.00
How to reset variables in a sequence recognition automaton in vhdl? +0.02
Multiple begin end statement in verilog 0.00
How to expand a single bit to multi-bits depending on parameter in... +0.49
FPGA to PC data transfer with PCI EXPRESS 0.00
Verilog simulation output is wrong, binary to Gray converter 0.00
Fpga surrounding circuitry 0.00
Verilog primitives 0.00
correct use and design of gated clock in Verilog 0.00
registering and resetting the convolution output in verilog 0.00
combine bit in verilog 0.00