StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Oldfart

Rating
1517.06 (38,625th)

Reputation
3,017 (56,061st)

Page: 1 2 3 4 ... 7

Title	Δ
How to fetch coefficients from ROM (actually BlockRAM in FPGA) to u...	-0.02
System Verilog : wire input for bits part indexing	0.00
Unexpected result of Not operator in assignment	+2.37
VHDL LR shifter circular not updating	0.00
Is this a verilog race condition?	0.00
Low Pass Filters in FPGA's	0.00
d[7:0] is an input vector, which shows to be ZZ in the simulation w...	0.00
Error: driven via a port connection, is multiply driven	+1.87
why the ROM designed from distributed memory block in vivado can...	0.00
How to simplify inputs for a decoder in verilog hdl	0.00
Creating multiport block ram in Vivado + Verilog	0.00
why the LEDS remain the initial state after programming a flowing-l...	0.00
How can I fix this "syntax error, unexpected '=' "...	0.00
setting the output reg of one device to be the input of another dev...	0.00
Access Zynq BRAM from PS and PL	0.00
Jumping into states that it shouldnt	0.00
How to create ethernet port from fpga digital input-output pins?	0.00
Getting Error in verilog primitive output connection must be a scal...	0.00
Non blocking statements with delays	+2.40
Writing to a peripheral in Vivado and then outputting to a LED	0.00
How to interface Red Pitaya FPGA with server code using Vivado	-0.00
Vivado: Warning The clock pin x_reg.C is not reached by a timing cl...	0.00
Output is in undefined state	0.00
In Verilog, can a "for loop" be of variable size?	0.00
How can i writing test bench for multiple module?	0.00
How to read input stimuli from file in a loop in systemverilog test...	0.00
Creating a `RAM` chip in `Verilog` with single in/out data port	0.00
How to send Differential UART signals in C	0.00
Check setup/hold time violations dynamically in an instantiated Ver...	0.00
if you have a long signed array, can you break it up using wires?	-0.94
How can you output a constant value in Verilog?	-1.63
How to implement sequential logic that exceeds a clock cycle?	0.00
In Verilog, when using a for-loop within a sequential process, how...	0.00
Why do incomplete if statements create latches during synthesis in...	+0.49
Verilog: Naming convention	0.00
Verilog real stuck at wrong state	-0.52
Is it possible to allow multiple drivers on a wire?	+0.00
Verilog-Got Error for Force description when [] is included in targ...	0.00
Number of bits for a particular count of integer in Verilog	+1.25
posedge or negedge in the body of the loop	0.00
Verilog square wave with phase offset	0.00
Can FPGA Stratix 3 memory handle large amount of data?	0.00
How to add a LUT in VHDL to generate a sine	0.00
Verilog: How to have a signal which have specific delay after clock...	0.00
vivado block designer not updating RTL interface in block design af...	-0.03
i have some problem about current time in vhdl	+0.48
VHDL Multi-Process	0.00
How to read and write DDR memory in FPGA?	+0.44
In Vivado, how to instantiate a user defined "Block Diagram&qu...	+0.45
Verilog: How to deal with if conditions of wires?	+0.49