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Rating Stats for

Tudor Timi

Rating
1511.77 (59,550th)

Reputation
5,810 (28,161st)

Page: 1 2 3 ... 5

Title	Δ
Configuring a custom Gradle sourceSet using a closure	0.00
Two macros that "complete" eachother	0.00
Class type in System Verilog which can not be constructed and exten...	+1.10
Assertion for valid comes once in req-ack transaction	0.00
What is a virtual accessor?	0.00
Why has uvm_top disappeared?	0.00
Constraint on an array with same values group together	0.00
Implementing System verilog’s $value$plusargs() system function in...	0.00
Cadence IUS simulator options	-0.52
Constraint in a 2d pixel matrix	0.00
Can we have one uvm_reg_map connected to multiple sequencers	+0.48
Creating transition coverage bins using a queue or dynamically	0.00
If I have a fixed size array , how do I write a constraint so that...	0.00
Specman e: Can delay() get a variable as an input with time unit?	0.00
I need to gen several bools simultaneously	0.00
Specman e: Is there a way to know how many values there is in an en...	+0.50
What is the standard way to loop over the elements of multi-dimensi...	0.00
system verilog 2 dimensional dynamic array randomization	0.00
How is the conditions in an illegal_bin declaration interpreted?	+2.54
Specman/e constraint (for each in) iteration	0.00
verilog/systemverilog passing parameters upwards through generated...	0.00
Multidriven nets: Synthesis ok, Simulation fails	0.00
Sequence that writes to either one of two different registers, but...	0.00
Specman e: How driver's items queue can be locked from a sequen...	0.00
SystemVerilog Values not inside a typedef enum	0.00
Setting compiler args as list of string in new language plugin	+2.64
Randomize a queue of objects in systemverilog	0.00
ovm printer casting error	0.00
When can TLM peek fail?	0.00
Recursive and non-recursive property: Are these assertions equal?	0.00
Output open array as a formal argument in DPI-C	0.00
Unable to acccess dimensions of svOpenArrayHandle	0.00
Specman e: A sequence drives its BFM also its MAIN was not defined...	0.00
Specman e subtyping: How to refer to FALSE value of conditional fie...	0.00
e HVL (IEEE 1647): expect expression fails unexpectedly	0.00
e HVL (IEEE 1647): How to set 'X' value?	0.00
Can events be passed by reference in Systemverilog?	-1.32
How to make an empty datatype or conditional field in SystemVerilog	+0.11
How do I stack trace info in the case of SystemVerilog+C DPI calls?	+0.47
Crossing clock domain for rarly changing data	0.00
Why do I have to reverse the concatenation order for inputs and out...	0.00
Sum 2D array in constraints in system verilog	0.00
Testing workflow for small (i.e. one person) design in SystemVerilog	+0.49
uvm - override virtual task in extended class	+0.01
Error (10686): SystemVerilog error at file.sv(8): InstAddress has a...	0.00
Add the date of creation to a filename in SystemVerilog	+2.10
Optimizing the registerfile code in systemverilog	+0.31
Systemverilog Testbench how to deal with configurable number of int...	0.00
Error in system verilog 2012 Reference guide regarding non-blocking...	0.00
SysteVerilog, UVM uvm_reg_adapter. Is there way use uvm_sequences i...	0.00