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Rating Stats for

Tudor Timi

Rating
1511.77 (59,550th)

Reputation
5,810 (28,161st)

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Title	Δ
I just started using Emacs 24.3.1 with System Verilog and I want to...	-0.09
UVM: Driving clock through interface	0.00
UVM: Driving clock through interface	0.00
what is the difference between 'define as' to 'define a...	-0.07
do_compare has a result of 1 however .compare return value is 0	0.00
UVM print_config does not display values	0.00
Warning when setting uvm_reg values through a task	-0.14
System Verilog interface with different inputs	+4.24
Passing array from system verilog to VHDL	0.00
System Verilog Clocking block	+4.32
UVM testbench - What is the "UVM" way to connect two diff...	-2.79
Is it allowed to have two structs with the same name?	-2.75
Does specman support checking severity reduction today?	-0.06
How can we improve our compilation flow with Specman?	-0.06
Multi-threading in UVM	0.00
Why is compiling object-oriented SystemVerilog code so slow?	0.00
Systemverilog coverage bins	0.00
Using burst_read/write with register model	-0.06
SystemVerilog foreach syntax for looping through lower dimension of...	+4.35
concurrent assertion inside for-loop in system verilog	-0.06
are fork.. join statements allowed in functions in system verilog?	-3.58
Basic UVM sequence simulation query	0.00
How to control the order of UVM analysis port subscribers?	+4.04
Systemverilog random bit vector	0.00
What is 'cycle' in specman events	0.00
*** Warning: WARN_GEN_CFA_UNSUPPORTED: in specman , why do i get it...	+0.01
virtual interface in system verilog also dynamic array cannot be us...	-1.65
Blocking assignment to a logic inside task in sv	0.00
Memory allocation in system verilog for dynamic array - new() / ran...	+0.45
running UVM phases on multiple cores	0.00
Sequence item generating 'X' or unknown value	0.00
Inheritance-like feature for interfaces	-3.83
How to perform uvm_do_on without randomization?	+3.98
SVA:Clock gating during SV assertion	-3.58
UVM phase singletons	0.00
Why are these SystemVerilog processes not ending?	0.00
an editor for specman	-2.11
System verilog: Passing parameters to package	0.00
SystemVerilog array random seed of Shuffle function	0.00
malformed statement in verilog	0.00
Driving input signals combinatorially (in the same cycle) in UVM	0.00
Can UVM flag a bad command line argument?	+3.68
Is it good idea to declare config object in uvm_sequence_item	+3.94
Serial Testbenching and assertions with System-Verilog	-0.02