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Rating Stats for

Tudor Timi

Rating
1511.77 (59,550th)

Reputation
5,810 (28,161st)

Page: 1 2 3 4 5

Title	Δ
Nonblocking driver-sequencer model	0.00
uvm_config_db set issue	0.00
SystemVerilog: introspection for functional coverage	+2.32
UVM: connecting sequencer+monitor with a scoreboard	0.00
functional_coverage not showing proper result	0.00
Connecting monitor and scoreboard in UVM	0.00
System Verilog Initial process compilation error	+0.01
How to update regmodel with writes going from RTL blocks	0.00
Simulating simple System verilog mailbox code using ModelSim	0.00
Invoking write/read_reg vr_ad macro from a virtual sequence in Spec...	0.00
Implementing UVM Agent in slave mode	0.00
Driving two different sequence items in one interface	0.00
In Riviera-PRO how can I return non zero exit code if any assertion...	0.00
Can I access delayed value in SystemVerilog assertion	0.00
Assertion to verify a glitch in a signal	0.00
Access parent class variables from nested class	0.00
systemverilog, signal concatenation	0.00
How to convert a SystemVerilog interface to individual ports	+0.51
UVM Register Model: volatile register value change	0.00
How to check class randomized object result with its derived class...	0.00
what is the difference between automatic and static task,why we can...	+0.50
Specman Parametrized Unit	+0.51
Override sequence members from test	0.00
Array of interface instances of different types	+0.32
Specman debugging OS11 in gen	0.00
How to initialize clocking block signals at reset	0.00
Specman string: How to split a string to a list of its chars?	0.00
How to connect a checker to an arbitrarily instance?	0.00
How to use UVM factory's set_inst_override_by_name to override...	0.00
wait($time >1000); cannot work in system-verilog?	+0.31
How to access randomized sequence_item from another sequence?	+0.48
Specman coverage: How to cover range of values in a list?	0.00
Specman e : Conditional Constraint in config sequence	0.00
cross coverage of transition in functional coverage of sysem verilog	0.00
connecting VHDL port to system verilog interface definition in UVM	0.00
how to runtimely show call stack in system verilog?	+0.01
how to search string inside another string in system verilog?	+0.51
Verilog Synthesis Error : "Expecting Endmodule", when usi...	0.00
SystemVerilog data type map to VHDL	0.00
Specman e: Is there a way to constrain the amount of set bits in a...	-0.49
Specman e: How to disable coverage of an instances / units?	0.00
Where does get_and_drive come from?	0.00
I want to rewrite a vhdl that includes the ieee library ieee.std_lo...	0.00
Find unused variables	0.00
Specman e: How to constrain distribution of values inside list of l...	0.00
SystemVerilog DPI-C pointers	0.00
The interface port must be passed an actual interface : system veri...	0.00
Grab Transactions inside UVM_Sequencer Run Phase	0.00
Specman e: When colon equal sign ":=" should be used?	0.00
Specman e: How to use deep_copy on list of structs?	+0.04