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Rating Stats for

Tudor Timi

Rating
1511.77 (59,550th)

Reputation
5,810 (28,161st)

Page: 1 2 3 4 ... 5

Title	Δ
If a sequence occurs then a subsequence occurs within it in System-...	0.00
Distributivity of 'or' operation in SVA	0.00
uvm register write is stuck and never return	0.00
SVA assume/assertions for continuous data input	-0.28
Can there be two 'uvm_tlm_b_target_socket' and two correspo...	-0.02
coverpoint weight is not catching in simulator	0.00
How to cover latency between request and response	+0.49
How to mimic static constructor in SystemVerilog?	+2.29
How to write property for formal verification?	+0.04
How can unique-case violations be caught by or report to the test-b...	0.00
Comparing simulation performance	+0.50
How can I check that I am in the build_phase in the UVM?	-1.73
SystemVerilog Clocking Blocks in Bi-Directional Interface	0.00
How to generate two variables at the same time?	0.00
Concurrent Assertion - UVM test dependency	0.00
Precedence of chained unary operators in SVA assertions	0.00
Memory Allocation in SystemVerilog Class	-1.74
Printing failure message in a try else block	+0.46
soft constraint on list size is ignored. why?	0.00
How to write cover points for transition in systemverilog?	0.00
How to create a directory with specman	+0.52
Randomizing values in specman	-0.49
How is backdoor access for registers, physically implemented in a V...	+1.10
Rewrite long xor statement	+0.18
Can a thread re-start without being killed in systemverilog fork-jo...	-0.50
Specman On the Fly Generation: How to constrain a list whose values...	-0.49
enclosing unit using virtual sequence	+0.00
In Specman, determinant is not constrained by its when subtype attr...	0.00
sync to data occurrence in the same cycle	-0.00
Behavior of contradicting soft constraints	-0.25
Randomize dut parameters in system verilog	+0.51
Is there any method to know whether a member is declared random or...	+2.00
Is there any method to know whether a member is declared random or...	-2.00
Difference between "new" and "gen"	0.00
How SVUnit has been used?	+0.49
Specman beginner's questions	+0.00
How to use throughout operator in systemverilog assertions	0.00
test case hanging at start_item	+0.00
Syntactic category (awareness) of define-as-computed macro?	0.00
Randomization of a class object inside a class in SystemVerilog	+0.49
Get response from sequence to control virtual sequence	0.00
Is there a way to access user defined variables in vsfi file?	+0.48
Regex in SV or UVM	0.00
uvm connect analysis port using full path	0.00
usage for uvm_re_match function	0.00
Does shell affects the randomization produced by a seed	0.00
Verilog - how to negate an array?	+0.84
Error: "(vlog-2110) Illegal reference to net"	+0.28
Specman reflection: Generic method to copy list of any type	+0.50
How to parameterize a case statement with don't cares?	+1.28