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Rating Stats for

Tudor Timi

Rating
1511.77 (59,550th)

Reputation
5,810 (28,161st)

Page: 1 2 3 4 5

Title	Δ
Specman e: How to constrain 'all_different' to list of stru...	+0.04
Specman: How to print negative hexadecimals?	+0.13
trying a code to check expect statement in specman	0.00
UVM virtual sequencer: choose the right child sequencer	-3.96
scoreboard data check use of associative arrays as storage structure	+4.13
I would like to instantiate modules based on selection, how?	0.00
Generate Conditional Assignment Statements in Verilog	+0.61
Calculating a parameter in a loop generate block	+4.00
Calculating a parameter in a loop generate block	-4.00
Global randomization in systemverilog across tests	0.00
Specman UVM: What is the difference between access a register direc...	0.00
Specman e vr_ad: How to use read_reg_field?	+0.16
Is there a system task or pre-processor directive in SystemVerilog...	-3.44
UVM shared variables	-1.96
What does [`something] some_vector ; mean in verilog?	0.00
Groups inside structs	0.00
Installing UVM 1.2 in Questasim 10.2 windows	0.00
uvm set_inst_override for a sequence	0.00
how to nor two vectors in dataflow verilog?	+4.60
UVM: Split sequences onto different sub sequencers	-3.91
Specman DAC macro: How to define 2 inputs of different type (uint a...	0.00
Specman e: Is there a way to extend multiple kinds of a struct?	-0.05
Can Verilog/Systemverilog/VHDL be considered actor oriented program...	+2.50
Specman: Is there a way to access different variables by some index?	0.00
How to output a multidimensional array slice	-3.97
Generate block inside case statement in verilog or system verilog	0.00
Specman UVM: How update a value of a register when the value was wr...	+0.00
Output skew when using clocking blocks	0.00
specman issue with parsing quotation marks	+3.96
Specman e: All files start with the word "package" - what...	+0.14
when to use $rose system task with a signal in assertions	0.00
How can I make Modelsim exit with a specified exit code from System...	-3.38
instantiation name modification in verilog under generate block	0.00
Is there an efficient way to convert a set to a (list of) integers?	+0.08
copy an object to a handle in systemverilog	0.00
in UVM RAL, a reg defined as no reset value, but set/update a '...	0.00
SVA - Is there any way to check an variable variable pattern in a v...	0.00
Calling ModelSim commands from SystemVerilog	-3.49
How to use uvm_test_done objection in test sequence?	0.00
SystemVerilog: how to assert the signals internal to module?	0.00
Hiding an element in ClearCase	-3.34
Illegal to access non-static method questaSim	+0.45
SystemVerilog: implies operator vs. \|->	-4.09
comparing strings by lexicographical order in e/specman	-0.04
Ruby and SystemVerilog DPI	+3.96
SystemVerilog/Verilog: Is there a way to find the integer bit offse...	-2.18
SystemVerilog/Verilog: Is there a way to find the integer bit offse...	-2.18
SVA: Is it possible to disable SV property check from consequent si...	0.00
Why is the following statement not allowed in e	0.00
Illegal assignment to class mtiUvm.uvm_pkg::uvm_component	0.00