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Paebbels

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1478.68 (4,501,424th)
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7,598 (20,885th)
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Title Δ
implementing a 50ns delay in VHDL +0.53
Setting FPGA clock frequency using Timing Constraints 0.00
Array of IO in Xilinx constraints file [VHDL Spartan-6] 0.00
Implementation error in ISE for a Virtex-5 board 0.00
Is it possible to implement .NET-like attributes in Python? +0.55
Resolve multiple constant drivers for net Error 0.00
Is it possible to Flash Two devices using 2 JTAG connected to singl... 0.00
How can I locate inferred latches in Xilinx ISE? 0.00
How do I combine incoming data and character in VHDL? 0.00
How to make startup process in VHDL +2.72
PCI Root Complex BAR usage 0.00
VHDL Add specific elements from a column of a 2d array -1.74
Substatemachine -1.36
Can't run HC - SR04 Sensor (VHDL) +0.56
PCIe and flow control credits 0.00
IC design/verification with Python +0.54
Bundle statements in VHDL +0.59
Testing FPGA Designs at Different Levels +0.55
How to do a TRUE rescan of PCIe bus 0.00
VHDL : No comparison operator available at all (used in binary to t... 0.00
Is there a way to show variables in ISim? -0.42
New DCM CLK instantiation error? +0.58
What is the best way to discover the topology of PCIe bus and the n... 0.00
How to make the library work work? -1.33
VHDL create a vector of alternating zeros and ones +0.07
Instantiation of RAM in FPGAs using VHDL +0.04
FPGA simulation doesn't match actual performance 0.00
Instantiating a LUT and Initialising with a .coe for ModelSim/Quest... -0.71
Working of a Gray Code +0.39
Is it possible to reduce the space requirement of a tree of binary... -0.30
How to display the amount of errors that occured in a self-verifyin... -0.44
How to create a list of Tcl commands in a text file and then run it... 0.00
VHDL: Default values in a Finite State Machine -1.39
How can I write unsigned type to file in VHDL? 0.00
Xilinx ISE: Should I be concerned about warning Xst:653? 0.00
Where's the latch in my VHDL program? 0.00
Array of 1-bit-wide memory -0.44
What is the cause of Vivados 'synth 8-1027' error? 0.00
CRC Generator(sender) and Checker(receiver) - parallel implementati... 0.00
Put attributes into file possible? 0.00
Synthesizable multidimensional arrays in VHDL +0.53
Best way to modify strings in VHDL 0.00
Any example useage of a BSCANE2 primitive in Xilinx 7 series? (usin... 0.00
VHDL map for each bit in a vector -0.46
VHDL downto incorrect MSB +2.24
Powershell RegEX Folder Tree 0.00
VHDL for loop limit on clock cycle 0.00
What is Base Address Register (BAR) in PCIe? 0.00
How to suppress a 'missing termination character' warning i... 0.00
Multiply two 32-bit vectors 0.00