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Rating Stats for

Greg

Rating
1564.37 (4,856th)

Reputation
13,439 (10,732nd)

Page: 1 ... 5 6 7 8 9 ... 12

Title	Δ
Asynchronous reset mysteriously setting up output reg	+1.07
Passing a module name as parameter	0.00
Priority encoder in verilog	+1.08
Bind ignores ifdef it is enclosed in	0.00
Arithmetic Division in Verilog	0.00
I'm getting an expecting 'endmodule' error in Verilog	0.00
how to index a reg or memory in for-loop by for-variable?	+1.86
Verilog - how to negate an array?	+0.50
how can i used the output of the instentiated module in verilog?	-0.10
Verilog HDL Code control unit and test bench codes [ port sizes do...	0.00
better alternative on for loop verilog	0.00
How to use if statements in verilog	0.00
How To display different data on a tied anodes of 7 segment display	0.00
Combinational logic "IF" and "assign" statement...	0.00
Event on logic value change	-1.98
Shifting 2D array in Verilog	0.00
In SystemVerilog, can events be defined in ports	0.00
code for shift add unit	0.00
Incorrect (?) delay results in modelsim (Verilog)	+0.07
Semaphore in system verilog	0.00
Verilog sync counter	0.00
Can I synthesize a parameterized function in systemverilog where st...	0.00
Parameterized function errors	0.00
What is the improve way to multiplying by 15?	-1.51
left-justified text for pli call	-2.00
left-justified text for pli call	+2.00
Code for 8 point DCT using shifters and adders	0.00
VerilogHDL - Error connecting Array with non-Array expressions	+1.99
Code to add two 4-bit integers with verilog doesn't work. What...	0.00
SystemVerilog: How to create an interface which is an array of a si...	-0.08
How to dynamically reverse the bit position in verilog?	-0.44
How to use arithmetic shift & selector in verilog?	0.00
Verilog: ERROR:HDLCompiler:806	0.00
SystemVerilog Assertion Error : Illegal use of non-constant express...	0.00
About struct in system-verilog?	0.00
assign output array correctly	0.00
Issue with reading bus signal. Compare to my Modelsim DE 10.2c and...	0.00
systemVerilog: affecting local scope of a variable from a task	0.00
Error when trying to synthesize verilog code	+0.43
Up Down counter code	-0.00
Combinational loop in a program	0.00
Ones count system-verilog	+0.45
calculate how many times input is repeated verilog	0.00
Case statements in Verilog?	0.00
Bit wise 'AND' an array of registers in Verilog	0.00
Verilog multipler wont compile need help ASAP	0.00
Trying to invert binary image gives me full black screen	0.00
Fill 0's with 1's beetween two 1's (synthesizable)	+0.20
Why doesn't this multi-line macro (with \r\n line endings) work...	0.00
timescale definition in modelsim	-0.18